From patchwork Thu Oct 6 22:54:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Brice X-Patchwork-Id: 9365427 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7E7D6600C8 for ; Thu, 6 Oct 2016 23:15:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 67A5D29280 for ; Thu, 6 Oct 2016 23:15:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5C10929286; Thu, 6 Oct 2016 23:15:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7E4629280 for ; Thu, 6 Oct 2016 23:15:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936005AbcJFXPF (ORCPT ); Thu, 6 Oct 2016 19:15:05 -0400 Received: from p3plsmtpa12-02.prod.phx3.secureserver.net ([68.178.252.231]:46042 "EHLO p3plsmtpa12-02.prod.phx3.secureserver.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935974AbcJFXPE (ORCPT ); Thu, 6 Oct 2016 19:15:04 -0400 X-Greylist: delayed 1211 seconds by postgrey-1.27 at vger.kernel.org; Thu, 06 Oct 2016 19:15:04 EDT Received: from bricepc.corp.datasoft.com ([184.185.173.186]) by :SMTPAUTH: with SMTP id sHYQbmHQSgB5RsHYTbZolz; Thu, 06 Oct 2016 15:54:22 -0700 From: Aaron Brice To: david.russell@datasoft.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, aisheng.dong@nxp.com Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] sdhci-esdhc-imx: Correct two register accesses Date: Thu, 6 Oct 2016 15:54:17 -0700 Message-Id: <1475794457-17993-1-git-send-email-aaron.brice@datasoft.com> X-Mailer: git-send-email 2.7.4 X-CMAE-Envelope: MS4wfIJRvQDlhlH5GeDGCke84KhldwL6onmFYYABUsX+CZw9vM0/lsrJrycz6a7QZ2+A4FfZc8tIW9+DNgfW3cB3qCytRGOYIBLVAPMynWjMtn1o3Na5Wgu1 jMojSU6rsjf8pEbnaM2QIhQ/GOEaeSzcCv9Y8+J/67DPn/M6UjYp073DUjbTD83eGY1xGGYs47pEydjq8fOTqTi/M8bsRYKu6+tjPd4jzPnK15EI7HH9mz4z paCMoBqCdOgFOcbsNtJsqggDv5CWn6oPy040W4ntKeLSFci/VHGvoZArWoihIIXwQfRU/hfU8lt34/FKScYg1xBB7KiYQTwsHW0EbxFbSb0lqSN2Xj7fze6+ NVscLqtDeLTlosB14mad1lVD+DptyxBSLIz2uKCNINckHC3Q1Khom4VTwcVDc7Gi/a/5vIfwH8QwJPDZu4ETWZQI7mCR7A== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice Acked-by: Dong Aisheng --- drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1f54fd8..d61ef16 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 data; - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { + if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || + reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the @@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) esdhc_clrset_le(host, 0xffff, val, reg); } +static u8 esdhc_readb_le(struct sdhci_host *host, int reg) +{ + u8 ret; + u32 long_val; + + switch (reg) { + case SDHCI_HOST_CONTROL: + long_val = readl(host->ioaddr + reg); + + ret = long_val & SDHCI_CTRL_LED; + ret |= (long_val >> 5) & SDHCI_CTRL_DMA_MASK; + ret |= (long_val & ESDHC_CTRL_4BITBUS); + ret |= (long_val & ESDHC_CTRL_8BITBUS) << 3; + return ret; + } + + return readb(host->ioaddr + reg); +} + static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .read_b = esdhc_readb_le, .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le,