From patchwork Mon Oct 10 18:39:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Brice X-Patchwork-Id: 9369849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3F26160487 for ; Mon, 10 Oct 2016 18:40:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 29699285EE for ; Mon, 10 Oct 2016 18:40:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C8A1285F8; Mon, 10 Oct 2016 18:40:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D76F285EE for ; Mon, 10 Oct 2016 18:40:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750830AbcJJSkb (ORCPT ); Mon, 10 Oct 2016 14:40:31 -0400 Received: from p3plsmtpa11-04.prod.phx3.secureserver.net ([68.178.252.105]:57420 "EHLO p3plsmtpa11-04.prod.phx3.secureserver.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750708AbcJJSka (ORCPT ); Mon, 10 Oct 2016 14:40:30 -0400 Received: from bricepc.corp.datasoft.com ([184.185.173.186]) by :SMTPAUTH: with SMTP id tfUObWYNh01SHtfUUbUM6t; Mon, 10 Oct 2016 11:39:59 -0700 From: Aaron Brice To: adrian.hunter@intel.com, ulf.hansson@linaro.org, aisheng.dong@nxp.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dave Russell Subject: [PATCH v2] sdhci-esdhc-imx: Correct two register accesses Date: Mon, 10 Oct 2016 11:39:52 -0700 Message-Id: <1476124792-18441-1-git-send-email-aaron.brice@datasoft.com> X-Mailer: git-send-email 2.7.4 X-CMAE-Envelope: MS4wfDaHQtJhqWZl5AEMN+L/JYv6kT/9l2q8+8TWr9eRAG8JakphaPF/m85+WKQQhXC+AYTowDjTSbj3j5vMVgU1ZXdpp5CQ4FPiGvfbEtXWzT9UPXZnFDid KVsJ2WEeGv8cVmeIshX5ZdCajEqgOpcryXFKxJch32unjkZekoQl0S2mMhCiBGmrNYPNbhrc6FMb3g/3Ia2Ir7jELdTDo08RTtifJ2UxS96df0YaPc4EMbx0 6WEJcxOceKVf77kVqVYEskUsMtayrvXazmTd4AuJYzgq2VwZKy/xpOCZXS3/KsuIAnTO3dv+k6mA1wX3lXSupSgw7zThY8PFGvOeY7Zng4kM/z7JcCqOOCdn GhJBWQsTAG7AoRORY17G0OMPRC89Fc3TcH4R1SO3ydcNo3z3jr9H92hmv58PZ/OL5Sm/PGIOY5rlfvXcGWb9GBi2HD4a5Q== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice Acked-by: Dong Aisheng Acked-by: Adrian Hunter --- v1 -> v2: - rename long_val to val drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1f54fd8..7123ef9 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 data; - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { + if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || + reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the @@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) esdhc_clrset_le(host, 0xffff, val, reg); } +static u8 esdhc_readb_le(struct sdhci_host *host, int reg) +{ + u8 ret; + u32 val; + + switch (reg) { + case SDHCI_HOST_CONTROL: + val = readl(host->ioaddr + reg); + + ret = val & SDHCI_CTRL_LED; + ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; + ret |= (val & ESDHC_CTRL_4BITBUS); + ret |= (val & ESDHC_CTRL_8BITBUS) << 3; + return ret; + } + + return readb(host->ioaddr + reg); +} + static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .read_b = esdhc_readb_le, .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le,