From patchwork Fri Feb 24 08:22:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong Mao X-Patchwork-Id: 9589507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EAAAD6042B for ; Fri, 24 Feb 2017 08:22:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC0EC283E2 for ; Fri, 24 Feb 2017 08:22:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF674287A2; Fri, 24 Feb 2017 08:22:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B322283E2 for ; Fri, 24 Feb 2017 08:22:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751202AbdBXIW0 (ORCPT ); Fri, 24 Feb 2017 03:22:26 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:23997 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751005AbdBXIWZ (ORCPT ); Fri, 24 Feb 2017 03:22:25 -0500 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1637533958; Fri, 24 Feb 2017 16:22:20 +0800 Received: from mhfsdcap03.localdomain (10.17.3.153) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 24 Feb 2017 16:22:19 +0800 From: Yong Mao To: Ulf Hansson CC: Linus Walleij , Chaotian Jing , yong mao , Eddie Huang , Chunfeng Yun , , , , , Subject: [PATCH v1] mmc: mediatek: Fixed bug where clock frequency could be set wrong Date: Fri, 24 Feb 2017 16:22:07 +0800 Message-ID: <1487924527-22584-2-git-send-email-yong.mao@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487924527-22584-1-git-send-email-yong.mao@mediatek.com> References: <1487924527-22584-1-git-send-email-yong.mao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: yong mao This patch can fix two issues: Issue 1: The maximum value of clock divider is 0xff. Because the type of div is u32, div may be larger than max_div. In this case, we should use max_div to set the clock frequency. Issue 2: In previous code, we can not set the correct clock frequency when div equals 0xff. Signed-off-by: Yong Mao Signed-off-by: Chaotian Jing --- drivers/mmc/host/mtk-sd.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 07f3236..3174445 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -540,6 +540,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) u32 mode; u32 flags; u32 div; + u32 max_div; u32 sclk; if (!hz) { @@ -590,8 +591,18 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) sclk = (host->src_clk_freq >> 2) / div; } } + + /** + * The maximum value of div is 0xff. + * Check if the div is larger than max_div. + */ + max_div = 0xff; + if (div > max_div) { + div = max_div; + sclk = (host->src_clk_freq >> 2) / div; + } sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, - (mode << 8) | (div % 0xff)); + (mode << 8) | div); sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) cpu_relax();