From patchwork Thu Mar 16 10:32:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9627819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AFA986048C for ; Thu, 16 Mar 2017 10:38:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A138628675 for ; Thu, 16 Mar 2017 10:38:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95D5D28688; Thu, 16 Mar 2017 10:38:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B82228675 for ; Thu, 16 Mar 2017 10:38:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751321AbdCPKhq (ORCPT ); Thu, 16 Mar 2017 06:37:46 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:6604 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751279AbdCPKhp (ORCPT ); Thu, 16 Mar 2017 06:37:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 16 Mar 2017 03:37:07 -0700 Received: from HQMAIL108.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 16 Mar 2017 03:37:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 16 Mar 2017 03:37:22 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 16 Mar 2017 10:32:53 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Thu, 16 Mar 2017 10:32:53 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.151]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Thu, 16 Mar 2017 03:32:52 -0700 From: Jon Hunter To: Adrian Hunter , Ulf Hansson , Thierry Reding , Ritesh Harjani CC: , , , Jon Hunter Subject: [PATCH 2/2] mmc: tegra: Fix setting of Tegra SDHCI module clock Date: Thu, 16 Mar 2017 10:32:44 +0000 Message-ID: <1489660364-17698-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489660364-17698-1-git-send-email-jonathanh@nvidia.com> References: <1489660364-17698-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit a8e326a911d3 ("mmc: tegra: implement module external clock change") implemented the SDHCI 'set_clock' handler for Tegra in order to change the module clock for the Tegra SDHCI controller by using the CCF API clk_set_rate(). The problem is the clk_set_rate() may sleep and the 'set_clock' handler is always called from within the context of a spinlock. Hence, occasionally, 'scheduling while atomic' are seen. Fix this by moving the setting of the module clock to the new 'set_parent_clock' handler which is not called from within the context of a spinlock. Fixes: a8e326a911d3 ("mmc: tegra: implement module external clock change") Signed-off-by: Jon Hunter --- drivers/mmc/host/sdhci-tegra.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 20b6ff5b4af1..048f84e615d3 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -217,18 +217,25 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); } -static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +static void tegra_sdhci_set_parent_clock(struct sdhci_host *host, + unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); unsigned long host_clk; if (!clock) - return sdhci_set_clock(host, clock); + return; host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; - clk_set_rate(pltfm_host->clk, host_clk); + WARN_ON(clk_set_rate(pltfm_host->clk, host_clk)); host->max_clk = clk_get_rate(pltfm_host->clk); +} + +static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); sdhci_set_clock(host, clock); @@ -320,6 +327,7 @@ static const struct sdhci_ops tegra_sdhci_ops = { .read_w = tegra_sdhci_readw, .write_l = tegra_sdhci_writel, .set_clock = tegra_sdhci_set_clock, + .set_parent_clock = tegra_sdhci_set_parent_clock, .set_bus_width = tegra_sdhci_set_bus_width, .reset = tegra_sdhci_reset, .platform_execute_tuning = tegra_sdhci_execute_tuning, @@ -368,6 +376,7 @@ static const struct sdhci_ops tegra114_sdhci_ops = { .write_w = tegra_sdhci_writew, .write_l = tegra_sdhci_writel, .set_clock = tegra_sdhci_set_clock, + .set_parent_clock = tegra_sdhci_set_parent_clock, .set_bus_width = tegra_sdhci_set_bus_width, .reset = tegra_sdhci_reset, .platform_execute_tuning = tegra_sdhci_execute_tuning,