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Mon, 17 Apr 2017 11:39:28 +0000 From: Haibo Chen To: , , CC: Subject: [PATCH] mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card Date: Mon, 17 Apr 2017 19:45:38 +0800 Message-ID: <1492429538-14996-1-git-send-email-haibo.chen@nxp.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [192.158.241.86] X-ClientProxiedBy: HK2PR04CA0083.apcprd04.prod.outlook.com (10.170.154.155) To DB6PR0401MB2328.eurprd04.prod.outlook.com (10.168.54.153) X-MS-Office365-Filtering-Correlation-Id: 8cb0b1d3-27e0-4bbf-9c79-08d485866935 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:DB6PR0401MB2328; X-Microsoft-Exchange-Diagnostics: 1; DB6PR0401MB2328; 3:B5xLzNXdBfbIVQTpvVC7OyjLam7WnIXXHWbn6pSYmkcg5jvAMu3xqdlCIQ/Ej6m5qfYHkX3D07ycfwQCVwGW6d0Y5e3Vp7225QGzA2sFJBJinjO6F4Kp9ZPHQgwjNtwtct5qi3xOonLFVw5Q9ODyK37lyeaBsWw/ZW9f3VSk61QfQUAuWMOkapj2MRmCUHV5CvgJBMyazFmgtQiByYvUGL8WjfqK3TAkTIcEhnzRbDk2uN017GI+hcbSJv1iNlYQEXzg8h0StymGMiwEn4RT5EVLKZIi4aJDIzYSppKGWZGI76JYKYV9Y32vctCj3SIZ5CntUIYZ4iP2gsjDvwxcC3KSsoiWEeG7cFv9n1/84FI=; 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SD3.0 card need tuning. For SDR104 card, when system suspend in standby mode, and then resume back, the IO timing is still SDR104(tuned) which may result in card re-enumeration fail in low card speed(400khz) for some cards. And we did meet the issue that in certain probability, SDR104 card meet mmc command CRC/Timeout error when send CMD2 during mmc bus resume. This patch reset the tuning circuit when the ios timing is MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS, which means both mmc_power_up() and mmc_power_off() will reset the tuning circuit. Signed-off-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index abad67a..8960833 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -889,6 +889,28 @@ static void esdhc_set_strobe_dll(struct sdhci_host *host) } } +static void esdhc_reset_tuning(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); + u16 ctrl; + + /* Rest the tuning circurt */ + if (esdhc_is_usdhc(imx_data)) { + if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { + ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); + ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; + ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; + writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); + writel(0 << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); + } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { + ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); + ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; + writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); + } + } +} + static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { u32 m; @@ -932,6 +954,10 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) host->ops->set_clock(host, host->clock); esdhc_set_strobe_dll(host); break; + case MMC_TIMING_LEGACY: + default: + esdhc_reset_tuning(host); + break; } esdhc_change_pinstate(host, timing);