| Message ID | 1493805925-3644-1-git-send-email-benoit@wsystem.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@wsystem.com> wrote: > The eSDHC can only DMA from 32-bit-aligned addresses. > > This fixes the following test cases of mmc_test: > 11: Badly aligned write > 12: Badly aligned read > 13: Badly aligned multi-block write > 14: Badly aligned multi-block read > > Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR was for devices that cannot address high memory above 0xffffffff, rather than requiring a specific alignment. If this is indeed an address range problem rather than an alignment problem, are you sure it is the SD controller that is wrong here, rather than having a 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the latter case, the dma-ranges property in the parent bus should limit the addressing, not the device. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/05/2017 10:47, Arnd Bergmann wrote: > On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@wsystem.com> wrote: >> The eSDHC can only DMA from 32-bit-aligned addresses. >> >> This fixes the following test cases of mmc_test: >> 11: Badly aligned write >> 12: Badly aligned read >> 13: Badly aligned multi-block write >> 14: Badly aligned multi-block read >> >> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> > > Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR > was for devices that cannot address high memory above 0xffffffff, rather than > requiring a specific alignment. > > If this is indeed an address range problem rather than an alignment problem, > are you sure it is the SD controller that is wrong here, rather than having a > 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the > latter case, the dma-ranges property in the parent bus should limit > the addressing, not the device. No, this is the right description. This quirk really is about alignment, and not about address range. See: drivers/mmc/host/sdhci.h: >--- /* Controller can only DMA from 32-bit aligned addresses */ #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) <--- drivers/mmc/host/sdhci.c @ sdhci_prepare_data(): >--- offset_mask = 0; [...] if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) offset_mask = 3; [...] if (sg->offset & offset_mask) { DBG("Reverting to PIO because of bad alignment\n"); host->flags &= ~SDHCI_REQ_USE_DMA; break; } <--- Benoît -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, May 4, 2017 at 11:00 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote: > On 04/05/2017 10:47, Arnd Bergmann wrote: >> On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@wsystem.com> wrote: >>> The eSDHC can only DMA from 32-bit-aligned addresses. >>> >>> This fixes the following test cases of mmc_test: >>> 11: Badly aligned write >>> 12: Badly aligned read >>> 13: Badly aligned multi-block write >>> 14: Badly aligned multi-block read >>> >>> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> >> >> Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR >> was for devices that cannot address high memory above 0xffffffff, rather than >> requiring a specific alignment. >> >> If this is indeed an address range problem rather than an alignment problem, >> are you sure it is the SD controller that is wrong here, rather than having a >> 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the >> latter case, the dma-ranges property in the parent bus should limit >> the addressing, not the device. > > No, this is the right description. This quirk really is about alignment, and not > about address range. See: > > drivers/mmc/host/sdhci.h: >>--- > /* Controller can only DMA from 32-bit aligned addresses */ > #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) > <--- > > drivers/mmc/host/sdhci.c @ sdhci_prepare_data(): >>--- > offset_mask = 0; > [...] > if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) > offset_mask = 3; Ok, thanks for the clarification. I guess I should have checked this myself first. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 03/05/17 13:05, Benoît Thébaudeau wrote: > The eSDHC can only DMA from 32-bit-aligned addresses. > > This fixes the following test cases of mmc_test: > 11: Badly aligned write > 12: Badly aligned read > 13: Badly aligned multi-block write > 14: Badly aligned multi-block read > > Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> I would expect to see Acks from other sdhci-esdhc users. Nevertheless for sdhci: Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-esdhc.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h > index c4bbd74..e7893f2 100644 > --- a/drivers/mmc/host/sdhci-esdhc.h > +++ b/drivers/mmc/host/sdhci-esdhc.h > @@ -19,6 +19,7 @@ > */ > > #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ > + SDHCI_QUIRK_32BIT_DMA_ADDR | \ > SDHCI_QUIRK_NO_BUSY_IRQ | \ > SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ > SDHCI_QUIRK_PIO_NEEDS_DELAY | \ > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, May 3, 2017 at 7:05 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote: > The eSDHC can only DMA from 32-bit-aligned addresses. > > This fixes the following test cases of mmc_test: > 11: Badly aligned write > 12: Badly aligned read > 13: Badly aligned multi-block write > 14: Badly aligned multi-block read > > Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index c4bbd74..e7893f2 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h @@ -19,6 +19,7 @@ */ #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ + SDHCI_QUIRK_32BIT_DMA_ADDR | \ SDHCI_QUIRK_NO_BUSY_IRQ | \ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ SDHCI_QUIRK_PIO_NEEDS_DELAY | \
The eSDHC can only DMA from 32-bit-aligned addresses. This fixes the following test cases of mmc_test: 11: Badly aligned write 12: Badly aligned read 13: Badly aligned multi-block write 14: Badly aligned multi-block read Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> --- drivers/mmc/host/sdhci-esdhc.h | 1 + 1 file changed, 1 insertion(+)