From patchwork Mon Aug 21 10:38:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 9912059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F1E4C602A0 for ; Mon, 21 Aug 2017 10:53:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E25BA252D5 for ; Mon, 21 Aug 2017 10:53:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D71992876A; Mon, 21 Aug 2017 10:53:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 463E0252D5 for ; Mon, 21 Aug 2017 10:53:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752519AbdHUKxL (ORCPT ); Mon, 21 Aug 2017 06:53:11 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:32128 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752481AbdHUKxJ (ORCPT ); Mon, 21 Aug 2017 06:53:09 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 21 Aug 2017 19:53:07 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 96ABB6E5BE; Mon, 21 Aug 2017 19:53:07 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.41,408,1498489200"; d="scan'208";a="255178115" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 21 Aug 2017 19:53:04 +0900 From: Biju Das To: Ulf Hansson , Rob Herring , Mark Rutland , Wolfram Sang Cc: Simon Horman , Magnus Damm , Chris Paterson , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Biju Das Subject: [PATCH v2] mmc: renesas_sdhi: Add r8a7743/5 support Date: Mon, 21 Aug 2017 11:38:17 +0100 Message-Id: <1503311897-18807-1-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502710766-44361-1-git-send-email-biju.das@bp.renesas.com> References: <1502710766-44361-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das Reviewed-by: Wolfram Sang Acked-by: Rob Herring --- v1->v2 -Modified the listing SoC's description related to SoC with 1 Clock and 2 Clocks This patch is compiled and tested against linux next tag next-20170817. Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index 4fd8b7a..1e3106e 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -15,6 +15,8 @@ Required properties: "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC + "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC + "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC @@ -33,10 +35,9 @@ Required properties: If 2 clocks are specified by the hardware, you must name them as "core" and "cd". If the controller only has 1 clock, naming is not required. - Below is the number clocks for each supported SoC: - 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790 - R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796 - 2: R7S72100 + Most supported SoCs only have 1 clock. Devices which have more + than 1 clock are listed below: + 2: R7S72100" Optional properties: - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable