From patchwork Fri Jul 20 12:45:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 10537279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 62EB4603B5 for ; Fri, 20 Jul 2018 12:46:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 590A029446 for ; Fri, 20 Jul 2018 12:46:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4DDD0296C2; Fri, 20 Jul 2018 12:46:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E06F229446 for ; Fri, 20 Jul 2018 12:46:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390434AbeGTNeN (ORCPT ); Fri, 20 Jul 2018 09:34:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6228 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389740AbeGTNeM (ORCPT ); Fri, 20 Jul 2018 09:34:12 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 20 Jul 2018 05:46:13 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 20 Jul 2018 05:46:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 20 Jul 2018 05:46:03 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 20 Jul 2018 12:46:05 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 20 Jul 2018 12:46:05 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 20 Jul 2018 05:46:05 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 4/7] arm64: dts: Add Tegra186 sdmmc pinctrl voltage states Date: Fri, 20 Jul 2018 15:45:43 +0300 Message-ID: <1532090746-15863-5-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532090746-15863-1-git-send-email-avienamo@nvidia.com> References: <1532090746-15863-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra186. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..7669756 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -236,6 +237,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; status = "disabled"; }; @@ -247,6 +251,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc2_3v3>; + pinctrl-1 = <&sdmmc2_1v8>; status = "disabled"; }; @@ -258,6 +265,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc3_3v3>; + pinctrl-1 = <&sdmmc3_1v8>; status = "disabled"; }; @@ -368,6 +378,36 @@ <0 0x0c380000 0 0x10000>, <0 0x0c390000 0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch"; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc2_3v3: sdmmc2-3v3 { + pins = "sdmmc2-hv"; + power-source = ; + }; + + sdmmc2_1v8: sdmmc2-1v8 { + pins = "sdmmc2-hv"; + power-source = ; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; }; ccplex@e000000 {