From patchwork Mon Jul 23 10:08:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10539841 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A7415157A for ; Mon, 23 Jul 2018 10:09:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95EC2284FF for ; Mon, 23 Jul 2018 10:09:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A53A285B9; Mon, 23 Jul 2018 10:09:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30675284FF for ; Mon, 23 Jul 2018 10:09:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388237AbeGWLJy (ORCPT ); Mon, 23 Jul 2018 07:09:54 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40928 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388175AbeGWLJy (ORCPT ); Mon, 23 Jul 2018 07:09:54 -0400 Received: by mail-pf1-f194.google.com with SMTP id e13-v6so10747pff.7 for ; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=aafJerS+Wy98Bqo54iiJlRRZ4XSAOzDYKbZmcV904pGjNkYIXGPlN5ERHKshAVYb+P rBSye5CXK+IrnLSQNwvnPqy/SrWY9XFvGR96twNi3hVDMB92dIXj8Lp0UzcPOd9Du1z3 ugMc20CHPyUB9xiuV/yTi2YA0W/pcQgkmzycE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=W98SSvPxVqr2IK+XM0GS3qjAE34U4LCgp/3YHvZzindhMIyZbFAPFzwwK1PrzFOjyE VQ4RgcVo4wK6GLAeP1PGaHasB3w1i7XakUYdiv75JwWsFH4SwXxANKBJgoXw9qnVxBrT fOnbHSB0vW6VUD/cpopaI3xn5BaCOqnjUzKGfVeJ9BO3L2sJq/5nxZZPcHLd0p0tr6Za 8lxbCw/8RzsiE5Reg91UNfiUJQVZ3mOCCltPp5cmHH5QJG2h830H0QuhCeE69uYDfn5K S3hOg9xjjbOEjOT3AFkte2XtWVO3QWHtKFLmiWTuK9wNedmwH1nCvzWc/A8tMRyRJSFC j0Mg== X-Gm-Message-State: AOUpUlE23IGTc9fm/TOQE3E8xfDn2Ax3Z1a4uMStlibP6+D+wobnXwVu MsbH3DYL/zjLv5JbrOD6mkwh4g== X-Google-Smtp-Source: AAOMgpeGj6vysc0vE8BADSpgdQXoBJDDXsSN8FHAVGSp9NhbObNDyUuDKkGJG40D5rkwWeNeeO/7zQ== X-Received: by 2002:a65:6203:: with SMTP id d3-v6mr11649605pgv.420.1532340567315; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm13470698pfk.87.2018.07.23.03.09.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 03:09:26 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Mon, 23 Jul 2018 18:08:25 +0800 Message-Id: <1532340508-8749-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 15 ++++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ce71afa..5acea3d 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -956,6 +956,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { + u32 reg; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1070,7 +1071,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 16-bit Block Count + * register need to be set to zero, 32-bit Block Count register would + * be selected. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 23318ff..81aae07 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))