From patchwork Tue Jul 24 02:51:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10541321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 470BA112E for ; Tue, 24 Jul 2018 02:51:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3770E2873E for ; Tue, 24 Jul 2018 02:51:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BD0B28714; Tue, 24 Jul 2018 02:51:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF0F528789 for ; Tue, 24 Jul 2018 02:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388367AbeGXDzk (ORCPT ); Mon, 23 Jul 2018 23:55:40 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:33069 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388365AbeGXDzk (ORCPT ); Mon, 23 Jul 2018 23:55:40 -0400 Received: by mail-pf1-f193.google.com with SMTP id b17-v6so491317pfi.0 for ; Mon, 23 Jul 2018 19:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=txKumXrCwsJ2SBxzMOb/NbZpSTq91k1tqQrJZCO3LMM=; b=jAgXze0dSOw2UANSA7IwGq5NpfuKN4Nf/E0pten2rnmMdhVreDCpXlIEiVkk/Fv3ag wgCzpi1gRsfGnwmTV+IQLtGukfMPehZAa++vgBYG2Iu3il0VhaSHnOdexDq5DLgeV33q Se8mXgxA3Sn0UYxhYgDf49bnA6DQTiirhBfmc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=txKumXrCwsJ2SBxzMOb/NbZpSTq91k1tqQrJZCO3LMM=; b=FKVAnsAm1KMHJmcaDxFpbNLYhOMkE5UljrR2OX5V2YbzKAyPBU4MNwvnU03383vhxB O2KU52rFE2wrkMEkGnuzeuZENQOvCGWAEkBNJEGzOA7WB6ndqzn2AGMxFgJ1JK16vjIK Z35+tIqoHNOpawOhVpK8v+A5JxHwtsmVIhKY8AxqphRlAx9bkVgv0GrIylboJUUzudYN J1V4jLdEZW//e7ZVV8GPQJafNDEHgD4zFwh+YuqNmv+aWTJSYnj6rRFSav4258oc0puO ofpea/ua7NAod+G+lV6bZypYqDHcL0ejYhZCso9UmpQIi7VSMqYlWef17G2hbLi2HLtr XQcg== X-Gm-Message-State: AOUpUlHnzPm0K4KZOnMpVJkbnE0PwckyCJbWYNJnHGMMqDk46uOmJ6N1 Mt4hW8HtSxVTNBwtruvvNpbulg== X-Google-Smtp-Source: AAOMgpdrPug9ZVEM4BCmvIUvDupVO4ZtfZb0J1uuLzcnnsGXStxBmXXRG1eIzhwfh/Gd9RDcqg3Q1A== X-Received: by 2002:a62:c4c3:: with SMTP id h64-v6mr15714313pfk.39.1532400688351; Mon, 23 Jul 2018 19:51:28 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id y132-v6sm14770373pfb.91.2018.07.23.19.51.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 19:51:27 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Tue, 24 Jul 2018 10:51:11 +0800 Message-Id: <1532400671-23429-1-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-5-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-5-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 920d8ec..c272a2b 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1070,7 +1070,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 16-bit Block Count + * register need to be set to zero, 32-bit Block Count register would + * be selected. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 23318ff..81aae07 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))