Message ID | 1533141150-10511-40-git-send-email-avienamo@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
Return-Path: <linux-mmc-owner@kernel.org> Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 102B813B8 for <patchwork-linux-mmc@patchwork.kernel.org>; Wed, 1 Aug 2018 16:34:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2B8028746 for <patchwork-linux-mmc@patchwork.kernel.org>; Wed, 1 Aug 2018 16:34:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E6C2A28B1E; Wed, 1 Aug 2018 16:34:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84C2D28746 for <patchwork-linux-mmc@patchwork.kernel.org>; Wed, 1 Aug 2018 16:34:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404078AbeHASVO (ORCPT <rfc822;patchwork-linux-mmc@patchwork.kernel.org>); Wed, 1 Aug 2018 14:21:14 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5056 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403923AbeHASVN (ORCPT <rfc822;linux-mmc@vger.kernel.org>); Wed, 1 Aug 2018 14:21:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id <B5b61e1140003>; Wed, 01 Aug 2018 09:34:28 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:34:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 01 Aug 2018 09:34:41 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:34:41 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:34:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:34:40 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id <B5b61e11e0001>; Wed, 01 Aug 2018 09:34:40 -0700 From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, "Stefan Agner" <stefan@agner.ch> CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH 39/40] arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 Date: Wed, 1 Aug 2018 19:32:29 +0300 Message-ID: <1533141150-10511-40-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: <linux-mmc.vger.kernel.org> X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP |
Series |
Tegra SDHCI add support for HS200 and UHS signaling
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diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 3b2fe0d..6e9ef26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -248,6 +248,9 @@ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; nvidia,default-tap = <0x5>; nvidia,default-trim = <0xb>; + assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_PLLP_OUT0>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; status = "disabled"; }; @@ -299,6 +302,9 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_SDMMC4>; clock-names = "sdhci"; + assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, + <&bpmp TEGRA186_CLK_PLLC4_VCO>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; reset-names = "sdhci"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by setting the assigned-clocks device tree properties. pllc4 offer better jitter performance and should be used with higher speed modes like HS200 and HS400. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)