| Message ID | 1533650404-18125-5-git-send-email-avienamo@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra SDHCI support HS400 on Tegra210 and Tegra186 | expand |
On Tue, Aug 07, 2018 at 05:00:00PM +0300, Aapo Vienamo wrote: > Implement HS400 specific delay line calibration procedure. > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > --- > drivers/mmc/host/sdhci-tegra.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) Should this be before the previous patch in order to make sure the calibration is performed as soon as the feature is available. This is counting beans I guess, but it is technically possible for someone to get everything up to patch 3/8 and then get the corresponding changes in the DTS files to enable the mode and then have HS400 enabled without this calibration. Thierry > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index d81143b..d0b68b7 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -56,6 +56,12 @@ > #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 > #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 > > +#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 > +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) > + > +#define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc > +#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) > + > #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 > #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 > > @@ -584,6 +590,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 val) > sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); > } > > +static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) > +{ > + u32 reg; > + int err; > + > + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); > + reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; > + sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); Is this self-clearing? Or do we need to clear it manually in order for a subsequent calibration procedure to succeed? Thierry
On Thu, 9 Aug 2018 13:48:05 +0200 Thierry Reding <thierry.reding@gmail.com> wrote: > On Tue, Aug 07, 2018 at 05:00:00PM +0300, Aapo Vienamo wrote: > > Implement HS400 specific delay line calibration procedure. > > > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > > --- > > drivers/mmc/host/sdhci-tegra.c | 29 +++++++++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > Should this be before the previous patch in order to make sure the > calibration is performed as soon as the feature is available. This is > counting beans I guess, but it is technically possible for someone to > get everything up to patch 3/8 and then get the corresponding changes > in the DTS files to enable the mode and then have HS400 enabled without > this calibration. True. > > > > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > > index d81143b..d0b68b7 100644 > > --- a/drivers/mmc/host/sdhci-tegra.c > > +++ b/drivers/mmc/host/sdhci-tegra.c > > @@ -56,6 +56,12 @@ > > #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 > > #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 > > > > +#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 > > +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) > > + > > +#define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc > > +#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) > > + > > #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 > > #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 > > > > @@ -584,6 +590,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 val) > > sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); > > } > > > > +static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) > > +{ > > + u32 reg; > > + int err; > > + > > + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); > > + reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; > > + sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); > > Is this self-clearing? Or do we need to clear it manually in order for > a subsequent calibration procedure to succeed? Yes, the TRM states that this bit should not be cleared by software. -Aapo -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index d81143b..d0b68b7 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -56,6 +56,12 @@ #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 +#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) + +#define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc +#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) + #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 @@ -584,6 +590,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 val) sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); } +static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) +{ + u32 reg; + int err; + + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); + reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; + sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); + + /* 1 ms sleep, 5 ms timeout */ + err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, + reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), + 1000, 5000); + if (err) + dev_err(mmc_dev(host->mmc), + "HS400 delay line calibration timed out\n"); +} + static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { @@ -591,6 +615,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); bool set_default_tap = false; bool set_dqs_trim = false; + bool do_hs400_dll_cal = false; switch (timing) { case MMC_TIMING_UHS_SDR50: @@ -600,6 +625,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, break; case MMC_TIMING_MMC_HS400: set_dqs_trim = true; + do_hs400_dll_cal = true; break; case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: @@ -620,6 +646,9 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, if (set_dqs_trim) tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); + + if (do_hs400_dll_cal) + tegra_sdhci_hs400_dll_cal(host); } static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
Implement HS400 specific delay line calibration procedure. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)