From patchwork Thu Aug 30 08:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10581359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3EA95174C for ; Thu, 30 Aug 2018 08:22:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E7482B6E1 for ; Thu, 30 Aug 2018 08:22:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2255A2B781; Thu, 30 Aug 2018 08:22:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B50122B6E1 for ; Thu, 30 Aug 2018 08:22:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728052AbeH3MXT (ORCPT ); Thu, 30 Aug 2018 08:23:19 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44497 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728048AbeH3MXS (ORCPT ); Thu, 30 Aug 2018 08:23:18 -0400 Received: by mail-pg1-f194.google.com with SMTP id r1-v6so3553803pgp.11 for ; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=W6ReI4x1Bc/JmVCF489DBl573vArOUp3cJURvJx9EXcspdw1VS15ynJVuAHRR1exLj x1PjZQ87eAHftm6Wv/LTZk1KuUzvimrJ4PNbshzliEbuMSZg9ESuN57vAAc7G3iLJ4Jz CYvAr9lGj8h1xuaJO2bIJ1CHUu9Cr1+Jp9WkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=ko3M5rdG8IOQxLlLw7/U9mOX/CyRd8pi1GEC4XmmUikc1RDfrkMW4NohRAH9oiAfMz 6ntuaoVj3w3UOLtFsW2uAeqOf9ZQyAvhf/Peko8GdWWWgH+9qWDY266sG/8Q37lgUGPq Cx/A9+/7DY+8fRKf7rg0MpYZlZBUasK/8s0KeKlXvYxG3YxcwLAxPNIcm4ChN/e/n6TS 9qGiCCsj0yvhEuP1Lmf/kMCAVv+8QF8fmFLnTayHRzKc5UWe3ldWSlTPmzI4xNDuNG0z hPv65kNYWX/qxtzlsryaPA/B8Z+EhhpXx9Sskacmec21DENEIeybSovjFh6oKG5lG67U PCaA== X-Gm-Message-State: APzg51BTiUaNxx+ytZ63XgF4soEN713DiWdisib080rYSCP0RqwIfUhQ MMui/kwKURiLE5d9GdIojAWcuQ== X-Google-Smtp-Source: ANB0VdYBCoLBFd/djSUyL8vhmwff4LDw2imhqvGfKmtHUobEqkY19rpLtRbAkGba8SeBdt2LLoDJgA== X-Received: by 2002:a62:9541:: with SMTP id p62-v6mr9585423pfd.194.1535617340445; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:19 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Thu, 30 Aug 2018 16:21:41 +0800 Message-Id: <1535617305-16952-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */