From patchwork Sat Sep 29 02:29:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaotian Jing X-Patchwork-Id: 10620593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63A9E15A6 for ; Sat, 29 Sep 2018 02:30:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E5432BD2F for ; Sat, 29 Sep 2018 02:30:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 622FA2BD44; Sat, 29 Sep 2018 02:30:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F5B72BD2F for ; Sat, 29 Sep 2018 02:30:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726325AbeI2I4v (ORCPT ); Sat, 29 Sep 2018 04:56:51 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:59682 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727355AbeI2I4u (ORCPT ); Sat, 29 Sep 2018 04:56:50 -0400 X-UUID: 0677bb2924024f129c3e3487994d181e-20180929 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 455522438; Sat, 29 Sep 2018 10:30:04 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 29 Sep 2018 10:30:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sat, 29 Sep 2018 10:30:01 +0800 From: Chaotian Jing To: Ulf Hansson CC: Rob Herring , Mark Rutland , Matthias Brugger , Chaotian Jing , Ryder Lee , Wolfram Sang , Sean Wang , , , , , , Subject: [PATCH v1 2/2] mmc: mediatek: add bus_clk control Date: Sat, 29 Sep 2018 10:29:55 +0800 Message-ID: <1538188195-3608-2-git-send-email-chaotian.jing@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1538188195-3608-1-git-send-email-chaotian.jing@mediatek.com> References: <1538188195-3608-1-git-send-email-chaotian.jing@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CDF554A6A90584992D63062400167C931FBC488D909A985C62635BD44C11D7622000:8 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP when gate MSDC0_HCLK, access register will hang, even the MSDC driver will never accessing register after HCLK was gated, but for safety, need gate the bus_clk(which used to access register) too. Signed-off-by: Chaotian Jing --- drivers/mmc/host/mtk-sd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 0484138..1c1c967 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -387,6 +387,7 @@ struct msdc_host { struct clk *src_clk; /* msdc source clock */ struct clk *h_clk; /* msdc h_clk */ + struct clk *bus_clk; /* bus clock which used to access register */ struct clk *src_clk_cg; /* msdc source clock control gate */ u32 mclk; /* mmc subsystem clock frequency */ u32 src_clk_freq; /* source clock frequency */ @@ -660,12 +661,14 @@ static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); clk_disable_unprepare(host->src_clk); + clk_disable_unprepare(host->bus_clk); clk_disable_unprepare(host->h_clk); } static void msdc_ungate_clock(struct msdc_host *host) { clk_prepare_enable(host->h_clk); + clk_prepare_enable(host->bus_clk); clk_prepare_enable(host->src_clk); clk_prepare_enable(host->src_clk_cg); while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) @@ -1900,6 +1903,9 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(host->bus_clk)) + host->bus_clk = NULL; /*source clock control gate is optional clock*/ host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); if (IS_ERR(host->src_clk_cg))