From patchwork Sat Mar 2 05:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10836459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C5AA17E0 for ; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A83F2D759 for ; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E9902D789; Sat, 2 Mar 2019 05:21:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEAEA2D759 for ; Sat, 2 Mar 2019 05:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727428AbfCBFVN (ORCPT ); Sat, 2 Mar 2019 00:21:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9841 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728120AbfCBFU4 (ORCPT ); Sat, 2 Mar 2019 00:20:56 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:21:04 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:55 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:55 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 2 Mar 2019 05:20:55 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:55 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:54 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 09/11] mmc: cqhci: add CQHCI_SSC1 register CBC field mask Date: Fri, 1 Mar 2019 21:20:23 -0800 Message-ID: <1551504025-3541-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504064; bh=wkx3HuTJxIWb28BfsCb9mlzWzWFwJ4pnX4Z3RHL7NaQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cnAZ9UVaGYuv0VtH4efT6tOehUYcwsVVjfb87WvWQC2whKsdqoswASKC0jqGeWCXU vCznwDwAp3D0KfwDocygT+FZdRECpGC3OTyontolHFV1ZqlgpDQc4snKjRjT+T27j2 kvtwZqFuinZn1pvCc6TaHWohTQpKqXRsr5rT03HBRIZePApImfpM8Mwb/8gvc95bvX VE4Rjwu/hifyw3T/aUn4giBQN4D1TfXyGX8G4tX+FYVP2zUKR7pHSU9fvb23LmainE pHWO6b31A0fzHAVXiXi79S8ZUKM/J+S4/1VZbYEy9n88oLczbdwY5moanzH7j/gnwL DU/rWcQPlVBfA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds define for CBC field mask of the register CQHCI_SSC1. Signed-off-by: Sowjanya Komatineni Acked-by: Adrian Hunter --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index f96d8565cc07..f1dc48c7436f 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -88,6 +88,7 @@ /* send status config 1 */ #define CQHCI_SSC1 0x40 +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) /* send status config 2 */ #define CQHCI_SSC2 0x44