From patchwork Mon Mar 11 18:02:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10847937 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BCA66C2 for ; Mon, 11 Mar 2019 18:03:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4984329291 for ; Mon, 11 Mar 2019 18:03:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D8D7292C8; Mon, 11 Mar 2019 18:03:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2F0229291 for ; Mon, 11 Mar 2019 18:03:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727727AbfCKSCm (ORCPT ); Mon, 11 Mar 2019 14:02:42 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9758 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfCKSCm (ORCPT ); Mon, 11 Mar 2019 14:02:42 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 11 Mar 2019 11:02:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 11 Mar 2019 11:02:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 11 Mar 2019 11:02:41 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 11 Mar 2019 18:02:41 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 11 Mar 2019 18:02:41 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.53]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 11 Mar 2019 11:02:40 -0700 From: Sowjanya Komatineni To: , , , , CC: , , , , , , Subject: [PATCH V2 01/10] mmc: tegra: fix ddr signaling for non-ddr modes Date: Mon, 11 Mar 2019 11:02:30 -0700 Message-ID: <1552327359-8036-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1552327362; bh=hyG6nL5bNLc49xU60zbU/EdhEZ33+W/EFOQiFZDWv4I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=Uif9OQr4GxsnnHw8J8F+zVWoQOemuKx9tqoAOg4mxvwPlBESbF5P1U74ezfS2e57y yU2EZ71jleL2jyePwNZea+dTi9jM0oDor2XZ2u6EVGVoEQdEyqLTn2g0R6KMd/80HC +K/0xjYgAv4nL+mdcqSpmjAJRqiRM3qTi1xcEEj7LSdJYyaEHIMiVO0o0i1OOd4Iou c81f2Q13rwbb28LTAVz1VClr7vnVc6538XI3C+zqFOlTRhw4HC4IvIXSBrydYVW2q0 WJNuyoQDKtUROtUC8VJXTctOGcM7mjMznAD5TqPPlGVQiAR5MBllX1gOcOQC7Yu73f P0/F6e+cx0UFQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 32e62904c0d3..46086dd43bfb 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, bool set_dqs_trim = false; bool do_hs400_dll_cal = false; + tegra_host->ddr_signaling = false; switch (timing) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: