| Message ID | 1581077075-26011-1-git-send-email-vbadigan@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V2] mmc: sdhci-msm: Don't enable PWRSAVE_DLL for certain sdhc hosts | expand |
On 2020-02-07 20:04, Veerabhadrarao Badiganti wrote: > From: Ritesh Harjani <riteshh@codeaurora.org> > > SDHC core with new 14lpp and later tech DLL should not enable > PWRSAVE_DLL since such controller's internal gating cannot meet > following MCLK requirement: > When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK > must be switched on for at-least 1us before DATA starts coming. > > Adding support for this requirement. > > Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> > Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> > -- Reviewed-by: Can Guo <cang@codeaurora.org> > > Changes since V1: > Condition was not correct in V1, which is corrected in V2 > > -- > --- > drivers/mmc/host/sdhci-msm.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c > b/drivers/mmc/host/sdhci-msm.c > index c3a160c..aa5b610 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -977,9 +977,21 @@ static int > sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) > goto out; > } > > - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); > - config |= CORE_PWRSAVE_DLL; > - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); > + /* > + * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. > + * When MCLK is gated OFF, it is not gated for less than 0.5us > + * and MCLK must be switched on for at-least 1us before DATA > + * starts coming. Controllers with 14lpp and later tech DLL cannot > + * guarantee above requirement. So PWRSAVE_DLL should not be > + * turned on for host controllers using this DLL. > + */ > + if (!msm_host->use_14lpp_dll_reset) { > + config = readl_relaxed(host->ioaddr + > + msm_offset->core_vendor_spec3); > + config |= CORE_PWRSAVE_DLL; > + writel_relaxed(config, host->ioaddr + > + msm_offset->core_vendor_spec3); > + } > > /* > * Drain writebuffer to ensure above DLL calibration
On 7/02/20 2:04 pm, Veerabhadrarao Badiganti wrote: > From: Ritesh Harjani <riteshh@codeaurora.org> > > SDHC core with new 14lpp and later tech DLL should not enable > PWRSAVE_DLL since such controller's internal gating cannot meet > following MCLK requirement: > When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK > must be switched on for at-least 1us before DATA starts coming. > > Adding support for this requirement. > > Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> > Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > -- > > Changes since V1: > Condition was not correct in V1, which is corrected in V2 > > -- > --- > drivers/mmc/host/sdhci-msm.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index c3a160c..aa5b610 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -977,9 +977,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) > goto out; > } > > - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); > - config |= CORE_PWRSAVE_DLL; > - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); > + /* > + * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. > + * When MCLK is gated OFF, it is not gated for less than 0.5us > + * and MCLK must be switched on for at-least 1us before DATA > + * starts coming. Controllers with 14lpp and later tech DLL cannot > + * guarantee above requirement. So PWRSAVE_DLL should not be > + * turned on for host controllers using this DLL. > + */ > + if (!msm_host->use_14lpp_dll_reset) { > + config = readl_relaxed(host->ioaddr + > + msm_offset->core_vendor_spec3); > + config |= CORE_PWRSAVE_DLL; > + writel_relaxed(config, host->ioaddr + > + msm_offset->core_vendor_spec3); > + } > > /* > * Drain writebuffer to ensure above DLL calibration >
On Fri, 7 Feb 2020 at 13:05, Veerabhadrarao Badiganti <vbadigan@codeaurora.org> wrote: > > From: Ritesh Harjani <riteshh@codeaurora.org> > > SDHC core with new 14lpp and later tech DLL should not enable > PWRSAVE_DLL since such controller's internal gating cannot meet > following MCLK requirement: > When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK > must be switched on for at-least 1us before DATA starts coming. > > Adding support for this requirement. > > Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> > Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Applied for next, thanks! Kind regards Uffe > -- > > Changes since V1: > Condition was not correct in V1, which is corrected in V2 > > -- > --- > drivers/mmc/host/sdhci-msm.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index c3a160c..aa5b610 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -977,9 +977,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) > goto out; > } > > - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); > - config |= CORE_PWRSAVE_DLL; > - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); > + /* > + * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. > + * When MCLK is gated OFF, it is not gated for less than 0.5us > + * and MCLK must be switched on for at-least 1us before DATA > + * starts coming. Controllers with 14lpp and later tech DLL cannot > + * guarantee above requirement. So PWRSAVE_DLL should not be > + * turned on for host controllers using this DLL. > + */ > + if (!msm_host->use_14lpp_dll_reset) { > + config = readl_relaxed(host->ioaddr + > + msm_offset->core_vendor_spec3); > + config |= CORE_PWRSAVE_DLL; > + writel_relaxed(config, host->ioaddr + > + msm_offset->core_vendor_spec3); > + } > > /* > * Drain writebuffer to ensure above DLL calibration > -- > Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index c3a160c..aa5b610 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -977,9 +977,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) goto out; } - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); - config |= CORE_PWRSAVE_DLL; - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); + /* + * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. + * When MCLK is gated OFF, it is not gated for less than 0.5us + * and MCLK must be switched on for at-least 1us before DATA + * starts coming. Controllers with 14lpp and later tech DLL cannot + * guarantee above requirement. So PWRSAVE_DLL should not be + * turned on for host controllers using this DLL. + */ + if (!msm_host->use_14lpp_dll_reset) { + config = readl_relaxed(host->ioaddr + + msm_offset->core_vendor_spec3); + config |= CORE_PWRSAVE_DLL; + writel_relaxed(config, host->ioaddr + + msm_offset->core_vendor_spec3); + } /* * Drain writebuffer to ensure above DLL calibration