| Message ID | 1590488522-9292-2-git-send-email-haibo.chen@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] mmc: sdhci-esdhc-imx: fix the mask for tuning start point | expand |
On Tue, 26 May 2020 at 12:32, <haibo.chen@nxp.com> wrote: > > From: Haibo Chen <haibo.chen@nxp.com> > > In current code, we add 1ms dealy after each tuning command for standard > tuning method. Adding this 1ms dealy is because USDHC default check the > CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning > IC logic do not wait for the tuning data sending out by the card, trigger > the buffer read ready interrupt immediately, and step to next cycle. So > when next time the new tuning command send out by USDHC, card may still > not send out the tuning data of the upper command，then some eMMC cards > may stuck, can't response to any command, block the whole tuning procedure. > > If do not check the CMD CRC for tuning, then do not has this issue. USDHC > will wait for the tuning data of each tuning command and check them. If the > tuning data pass the check, it also means the CMD line also okay for tuning. > > So this patch disable the CMD CRC check for tuning, save some time for the > whole tuning procedure. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-esdhc-imx.c | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c > index 2cf7fa59270e..b0ddf3db440f 100644 > --- a/drivers/mmc/host/sdhci-esdhc-imx.c > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c > @@ -91,6 +91,7 @@ > /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ > #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 > #define ESDHC_TUNING_START_TAP_MASK 0x7f > +#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) > #define ESDHC_TUNING_STEP_MASK 0x00070000 > #define ESDHC_TUNING_STEP_SHIFT 16 > > @@ -1316,6 +1317,18 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) > tmp |= imx_data->boarddata.tuning_step > << ESDHC_TUNING_STEP_SHIFT; > } > + > + /* Disable the CMD CRC check for tuning, if not, need to > + * add some delay after every tuning command, because > + * hardware standard tuning logic will directly go to next > + * step once it detect the CMD CRC error, will not wait for > + * the card side to finally send out the tuning data, trigger > + * the buffer read ready interrupt immediately. If usdhc send > + * the next tuning command some eMMC card will stuck, can't > + * response, block the tuning procedure or the first command > + * after the whole tuning procedure always can't get any response. > + */ > + tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; > writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); > } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { > /* > @@ -1661,8 +1674,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) > if (err) > goto disable_ahb_clk; > > - host->tuning_delay = 1; > - > sdhci_esdhc_imx_hwinit(host); > > err = sdhci_add_host(host); > -- > 2.17.1 >
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 2cf7fa59270e..b0ddf3db440f 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -91,6 +91,7 @@ /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 #define ESDHC_TUNING_START_TAP_MASK 0x7f +#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) #define ESDHC_TUNING_STEP_MASK 0x00070000 #define ESDHC_TUNING_STEP_SHIFT 16 @@ -1316,6 +1317,18 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) tmp |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT; } + + /* Disable the CMD CRC check for tuning, if not, need to + * add some delay after every tuning command, because + * hardware standard tuning logic will directly go to next + * step once it detect the CMD CRC error, will not wait for + * the card side to finally send out the tuning data, trigger + * the buffer read ready interrupt immediately. If usdhc send + * the next tuning command some eMMC card will stuck, can't + * response, block the tuning procedure or the first command + * after the whole tuning procedure always can't get any response. + */ + tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { /* @@ -1661,8 +1674,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (err) goto disable_ahb_clk; - host->tuning_delay = 1; - sdhci_esdhc_imx_hwinit(host); err = sdhci_add_host(host);