From patchwork Mon Jul 20 00:42:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 11672713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B489E1510 for ; Mon, 20 Jul 2020 00:43:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BFE522CAE for ; Mon, 20 Jul 2020 00:43:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="rvlvlbUc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726508AbgGTAnG (ORCPT ); Sun, 19 Jul 2020 20:43:06 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:46765 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726577AbgGTAmy (ORCPT ); Sun, 19 Jul 2020 20:42:54 -0400 X-UUID: 0cd6a751f3a14a51a82852678aed2b43-20200720 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=juG6BnX41+DeE6Q27S76GMbkvGJcmbG29m+dVuuEOXo=; b=rvlvlbUcUREd56eWXcM+xZM9O/VGdEbe9/5ysKIOjaBSPx6FRASQ6Y65aOcDtO+/yABGBGtnTTWvuivmW2AwaREvE94A464EHlKfCHOYOaO0byar/VZVEuTWITCVWqQq5VPjhLrCncVKocw1/RwdSH//J9U7ZyPCuRMwZRRA/Ek=; X-UUID: 0cd6a751f3a14a51a82852678aed2b43-20200720 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 841372942; Mon, 20 Jul 2020 08:42:45 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 20 Jul 2020 08:42:43 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 20 Jul 2020 08:42:43 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH v7 2/4] mmc: mediatek: refine msdc timeout api Date: Mon, 20 Jul 2020 08:42:37 +0800 Message-ID: <1595205759-5825-3-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1595205759-5825-1-git-send-email-chun-hung.wu@mediatek.com> References: <1595205759-5825-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: C4513997F2F8320F12D325293F26DF128DB1966A082367BFE74571B7E9C474092000:8 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Extract msdc timeout api common part to have better code architecture and avoid redundant code. Signed-off-by: Chun-Hung Wu Reviewed-by: Matthias Brugger --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index ed37a3c..347ed72 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -723,21 +723,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -747,9 +747,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host)