| Message ID | 1649670615-21268-8-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SDX65 devicetree updates | expand |
On Mon 11 Apr 04:50 CDT 2022, Rohit Agarwal wrote: > Add smem node to support shared memory manager on SDX65 platform. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 210e55c..8fef644 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -113,6 +113,12 @@ > }; > }; > > + smem { > + compatible = "qcom,smem"; > + memory-region = <&smem_mem>; > + hwlocks = <&tcsr_mutex 3>; > + }; As you only have the single region, please move the compatible and hwlocks properties into the &smem_mem node (see sm8450.dtsi in arm64 as an example). I've applied the other dts changes. Thanks, Bjorn > + > soc: soc { > #address-cells = <1>; > #size-cells = <1>; > -- > 2.7.4 >
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 210e55c..8fef644 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -113,6 +113,12 @@ }; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>;
Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)