From patchwork Thu Nov 18 09:00:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chuanxiao.Dong" X-Patchwork-Id: 335361 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oAI92sGm010018 for ; Thu, 18 Nov 2010 09:02:54 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753539Ab0KRJCx (ORCPT ); Thu, 18 Nov 2010 04:02:53 -0500 Received: from mga02.intel.com ([134.134.136.20]:17505 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751808Ab0KRJCv convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 04:02:51 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 18 Nov 2010 01:02:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.59,216,1288594800"; d="scan'208,223";a="678678864" Received: from unknown (HELO intel.com) ([172.16.120.128]) by orsmga001.jf.intel.com with ESMTP; 18 Nov 2010 01:02:49 -0800 Date: Thu, 18 Nov 2010 17:00:35 +0800 From: Chuanxiao Dong To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, alan@linux.intel.com, arjan@linux.intel.com Subject: [PATCH v2 1/3]mmc:Add a new quirk for SDHCI HC to erase single erase block Message-ID: <20101118090035.GB18161@intel.com> Reply-To: Chuanxiao Dong MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 18 Nov 2010 09:02:54 +0000 (UTC) diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c index 4e42d03..f665c62 100644 --- a/drivers/mmc/card/queue.c +++ b/drivers/mmc/card/queue.c @@ -131,7 +131,13 @@ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, spinlock_t *lock queue_flag_set_unlocked(QUEUE_FLAG_NONROT, mq->queue); if (mmc_can_erase(card)) { queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, mq->queue); - mq->queue->limits.max_discard_sectors = UINT_MAX; + /* get a suitable max_discard_sectors limitation */ + ret = mmc_set_discard_limit(card); + if (ret > 0) + mq->queue->limits.max_discard_sectors = ret; + else + mq->queue->limits.max_discard_sectors = UINT_MAX; + if (card->erased_byte == 0) mq->queue->limits.discard_zeroes_data = 1; if (!mmc_can_trim(card) && is_power_of_2(card->erase_size)) { diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 434e62c..947d963 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1454,6 +1454,33 @@ int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from, } EXPORT_SYMBOL(mmc_erase_group_aligned); +/* + * mmc_set_discard_limit: set the max_discard_sectors according + * to host controller timeout capability. + */ +int mmc_set_discard_limit(struct mmc_card *card) +{ + struct mmc_host *host; + unsigned int nr = 0; + host = card->host; + if (host->caps & MMC_CAP_ERASE_SINGLE) { + /* + * Have to set a small limitation for request queue + * to ensure that host controller won't generate a + * timeout interrupt during waiting, here let limitation + * to be 1 erase block. And this will let TRIM/ERASE + * performance lower. + */ + nr = 1; + if (card->erase_shift) + nr <<= card->erase_shift; + else + nr *= card->erase_size; + } + return nr; +} +EXPORT_SYMBOL(mmc_set_discard_limit); + int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen) { struct mmc_command cmd; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 154cbf8..fa66988 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1857,6 +1857,10 @@ int sdhci_add_host(struct sdhci_host *host) mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; mmc->f_max = host->max_clk; mmc->caps |= MMC_CAP_SDIO_IRQ; + mmc->caps |= MMC_CAP_ERASE; + + if (host->quirks & SDHCI_QUIRK_FORCE_ERASE_SINGLE) + mmc->caps |= MMC_CAP_ERASE_SINGLE; if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 64e013f..ffddd1f 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -152,6 +152,7 @@ extern int mmc_can_trim(struct mmc_card *card); extern int mmc_can_secure_erase_trim(struct mmc_card *card); extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from, unsigned int nr); +extern int mmc_set_discard_limit(struct mmc_card *card); extern int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index f108cee..85df99a 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -168,6 +168,8 @@ struct mmc_host { /* DDR mode at 1.8V */ #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ /* DDR mode at 1.2V */ +#define MMC_CAP_ERASE_SINGLE (1 << 13) + /* Erase signle erase block each time */ mmc_pm_flag_t pm_caps; /* supported pm features */ diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 1fdc673..e7bdfc8 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -83,6 +83,8 @@ struct sdhci_host { #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) +/* Controller has an issue with erase/trim the whole device at one time */ +#define SDHCI_QUIRK_FORCE_ERASE_SINGLE (1<<30) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */