From patchwork Tue Feb 4 19:24:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?David_Lanzend=C3=B6rfer?= X-Patchwork-Id: 3578661 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0B0C4C02DC for ; Tue, 4 Feb 2014 19:33:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2D5FB201D3 for ; Tue, 4 Feb 2014 19:33:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AFE420181 for ; Tue, 4 Feb 2014 19:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752735AbaBDTde (ORCPT ); Tue, 4 Feb 2014 14:33:34 -0500 Received: from kolab.o2s.ch ([77.109.136.180]:58595 "EHLO kolab.o2s.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754756AbaBDTdd (ORCPT ); Tue, 4 Feb 2014 14:33:33 -0500 Received: from localhost (localhost [127.0.0.1]) by kolab.o2s.ch (Postfix) with ESMTP id 350547620D; Tue, 4 Feb 2014 20:28:15 +0100 (CET) X-Virus-Scanned: amavisd-new at example.com Received: from kolab.o2s.ch ([127.0.0.1]) by localhost (kolab.o2s.ch [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Um-nw3WDYD92; Tue, 4 Feb 2014 20:28:14 +0100 (CET) Received: from dizzy-6.o2s.ch (unknown [IPv6:2001:470:26:484:6ef0:49ff:fee6:8dca]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by kolab.o2s.ch (Postfix) with ESMTPSA id EAABC7620C; Tue, 4 Feb 2014 20:28:12 +0100 (CET) Subject: [PATCH v2 2/6] clk: sunxi: Implement MMC phase control To: devicetree@vger.kernel.org, Ulf Hansson , Laurent Pinchart , Simon Baatz , Hans de Goede , linux-mmc@vger.kernel.org, Chris Ball , linux-kernel@vger.kernel.org, H Hartley Sweeten , linux-sunxi@googlegroups.com, Tejun Heo , Maxime Ripard , Guennadi Liakhovetski , linux-arm-kernel@lists.infradead.org From: David =?utf-8?q?Lanzend=C3=B6rfer?= Date: Tue, 04 Feb 2014 20:24:50 +0100 Message-ID: <20140204192446.29809.66539.stgit@dizzy-6.o2s.ch> In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch> References: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Emilio López Signed-off-by: Emilio López --- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..33b9977 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, /** + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control + */ + +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output) +{ + #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) + #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) + + struct clk_composite *composite = to_clk_composite(hw); + struct clk_hw *rate_hw = composite->rate_hw; + struct clk_factors *factors = to_clk_factors(rate_hw); + unsigned long flags = 0; + u32 reg; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + reg = readl(factors->reg); + + /* set sample clock phase control */ + reg &= ~(0x7 << 20); + reg |= ((sample & 0x7) << 20); + + /* set output clock phase control */ + reg &= ~(0x7 << 8); + reg |= ((output & 0x7) << 8); + + writel(reg, factors->reg); + + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); +} + + +/** * sunxi_factors_clk_setup() - Setup function for factor clocks */