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[98.203.232.209]) by smtp.gmail.com with ESMTPSA id dj3sm54955142pad.1.2016.10.19.11.18.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 11:18:27 -0700 (PDT) From: Kevin Hilman To: Ulf Hansson , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 2/2] Documentation: DT: MMC: meson-gx: new bindings doc Date: Wed, 19 Oct 2016 11:18:25 -0700 Message-Id: <20161019181825.2186-2-khilman@baylibre.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161019181825.2186-1-khilman@baylibre.com> References: <20161019181825.2186-1-khilman@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Kevin Hilman Acked-by: Rob Herring --- .../devicetree/bindings/mmc/amlogic,meson-gx.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt new file mode 100644 index 000000000000..a2fa9a1c26ae --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt @@ -0,0 +1,33 @@ +Amlogic SD / eMMC controller for S905/GXBB family SoCs + +The MMC 5.1 compliant host controller on Amlogic provides the +interface for SD, eMMC and SDIO devices. + +This file documents the properties in addition to those available in +the MMC core bindings, documented by mmc.txt. + +Required properties: +- compatible : contains one of: + - "amlogic,meson-gx-mmc" + - "amlogic,meson-gxbb-mmc" + - "amlogic,meson-gxl-mmc" + - "amlogic,meson-gxm-mmc" +- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. +- clock-names: Should contain the following: + "core" - Main peripheral bus clock + "clkin0" - Parent clock of internal mux + "clkin1" - Other parent clock of internal mux + The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the + clock rate requested by the MMC core. + +Example: + + sd_emmc_a: mmc@70000 { + compatible = "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x70000 0x0 0x2000>; + interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + pinctrl-0 = <&emmc_pins>; + }; +