From patchwork Tue Jan 17 23:14:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 9522215 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47CF26043D for ; Tue, 17 Jan 2017 23:28:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E2FE2855A for ; Tue, 17 Jan 2017 23:28:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2FD7028569; Tue, 17 Jan 2017 23:28:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A273C28569 for ; Tue, 17 Jan 2017 23:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751769AbdAQX2q (ORCPT ); Tue, 17 Jan 2017 18:28:46 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:59254 "EHLO outils.crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751498AbdAQX2T (ORCPT ); Tue, 17 Jan 2017 18:28:19 -0500 From: Paul Cercueil To: Linus Walleij , Rob Herring , Mark Rutland , Ralf Baechle , Ulf Hansson , Boris Brezillon , Thierry Reding , Bartlomiej Zolnierkiewicz , Maarten ter Huurne , Lars-Peter Clausen , Paul Burton Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-mmc@vger.kernel.org, linux-mtd@lists.infradead.org, linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org, james.hogan@imgtec.com, Paul Cercueil Subject: [PATCH 05/13] MIPS: jz4740: DTS: Add node for the jz4740-pinctrl driver Date: Wed, 18 Jan 2017 00:14:13 +0100 Message-Id: <20170117231421.16310-6-paul@crapouillou.net> In-Reply-To: <20170117231421.16310-1-paul@crapouillou.net> References: <20170117231421.16310-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1484694904; bh=wOwgqNh6c4h+D5RFu7rgThF6j8Rxr4aWC1xU+G5vBNk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=PqZ2S0a9ffGOgIRDhBnh7x/idSNxsGt/hWEsuI9BxQHvUjr1XpGTese21OEzyyEiyqSpMKX+RoyZbpf+MMx4Px4gH0sie/NwQ8gzz+4w8sTYDYo7gxQM5eoivfoxn5XP+/cZxReVRyFshdWOxrFhCO/p+WyBqa4GEul36HnoiTg= Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For a description of the devicetree node, please read Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt Signed-off-by: Paul Cercueil --- arch/mips/boot/dts/ingenic/jz4740.dtsi | 275 +++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 3e1587f1f77a..c014a7159a2a 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -55,6 +55,281 @@ clock-names = "rtc"; }; + pinctrl: ingenic-pinctrl@10010000 { + compatible = "ingenic,jz4740-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio-chips { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpa: gpa { + reg = <0x10010000 0x100>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <28>; + + ingenic,pull-ups = <0xffffffff>; + }; + + gpb: gpb { + reg = <0x10010100 0x100>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <27>; + + ingenic,pull-ups = <0xffffffff>; + }; + + gpc: gpc { + reg = <0x10010200 0x100>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <26>; + + ingenic,pull-ups = <0xffffffff>; + }; + + gpd: gpd { + reg = <0x10010300 0x100>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <25>; + + ingenic,pull-ups = <0xdfffffff>; + }; + }; + + bias-configs { + nobias: pincfg-nobias { + bias-disable; + }; + + pull_up: pincfg-pull-up { + bias-pull-up; + }; + + pull_down: pincfg-pull-down { + bias-pull-down; + }; + }; + + functions { + pinfunc-msc { + pins_msc_4bit: pins-msc-4bit { + ingenic,pins = <&gpd 8 0 &nobias + &gpa 9 0 &nobias + &gpa 10 0 &nobias + &gpa 11 0 &nobias + &gpa 12 0 &nobias + &gpa 13 0 &nobias>; + }; + }; + + pinfunc-uart0 { + pins_uart0_data: pins-uart0-data { + ingenic,pins = <&gpd 26 1 &pull_up /* rxd */ + &gpd 25 1 &nobias>; /* txd */ + }; + + pins_uart0_dataplusflow: uart0-dataplusflow { + ingenic,pins = <&gpd 26 1 &pull_up /* rxd */ + &gpd 25 1 &nobias /* txd */ + &gpd 31 0 &nobias /* rts */ + &gpd 30 0 &nobias>; /* cts */ + }; + }; + + pinfunc-uart1 { + pins_uart1_data: uart1-data { + ingenic,pins = <&gpd 30 2 &pull_up /* rxd */ + &gpd 31 2 &nobias>; /* txd */ + }; + }; + + pinfunc-lcd { + pins_lcd_8bit: pins-lcd-8bit { + ingenic,pins = <&gpc 0 0 &nobias /* LCD_DATA0 */ + &gpc 1 0 &nobias + &gpc 2 0 &nobias + &gpc 3 0 &nobias + &gpc 4 0 &nobias + &gpc 5 0 &nobias + &gpc 6 0 &nobias + &gpc 7 0 &nobias /* LCD_DATA7 */ + &gpc 18 0 &nobias /* PCLK */ + &gpc 19 0 &nobias /* HSYNC */ + &gpc 20 0 &nobias>; /* VSYNC */ + }; + + pins_lcd_16bit: pins-lcd-16bit { + ingenic,pins = <&gpc 0 0 &nobias /* LCD_DATA0 */ + &gpc 1 0 &nobias + &gpc 2 0 &nobias + &gpc 3 0 &nobias + &gpc 4 0 &nobias + &gpc 5 0 &nobias + &gpc 6 0 &nobias + &gpc 7 0 &nobias + &gpc 8 0 &nobias + &gpc 9 0 &nobias + &gpc 10 0 &nobias + &gpc 11 0 &nobias + &gpc 12 0 &nobias + &gpc 13 0 &nobias + &gpc 14 0 &nobias + &gpc 15 0 &nobias /* LCD_DATA15 */ + &gpc 18 0 &nobias /* PCLK */ + &gpc 19 0 &nobias /* HSYNC */ + &gpc 20 0 &nobias /* VSYNC */ + &gpc 21 0 &nobias>; /* DE */ + }; + + pins_lcd_18bit: pins-lcd-18bit { + ingenic,pins = <&gpc 0 0 &nobias /* LCD_DATA0 */ + &gpc 1 0 &nobias + &gpc 2 0 &nobias + &gpc 3 0 &nobias + &gpc 4 0 &nobias + &gpc 5 0 &nobias + &gpc 6 0 &nobias + &gpc 7 0 &nobias + &gpc 8 0 &nobias + &gpc 9 0 &nobias + &gpc 10 0 &nobias + &gpc 11 0 &nobias + &gpc 12 0 &nobias + &gpc 13 0 &nobias + &gpc 14 0 &nobias + &gpc 15 0 &nobias + &gpc 16 0 &nobias + &gpc 17 0 &nobias /* LCD_DATA17 */ + &gpc 18 0 &nobias /* PCLK */ + &gpc 19 0 &nobias /* HSYNC */ + &gpc 20 0 &nobias /* VSYNC */ + &gpc 21 0 &nobias>; /* DE */ + }; + + pins_lcd_special_tft: pins-lcd-special-tft { + ingenic,pins = <&gpc 0 0 &nobias /* LCD_DATA0 */ + &gpc 1 0 &nobias + &gpc 2 0 &nobias + &gpc 3 0 &nobias + &gpc 4 0 &nobias + &gpc 5 0 &nobias + &gpc 6 0 &nobias + &gpc 7 0 &nobias + &gpc 8 0 &nobias + &gpc 9 0 &nobias + &gpc 10 0 &nobias + &gpc 11 0 &nobias + &gpc 12 0 &nobias + &gpc 13 0 &nobias + &gpc 14 0 &nobias + &gpc 15 0 &nobias + &gpc 16 0 &nobias + &gpc 17 0 &nobias /* LCD_DATA17 */ + &gpc 18 0 &nobias /* PCLK */ + &gpc 19 0 &nobias /* HSYNC */ + &gpc 20 0 &nobias /* VSYNC */ + &gpc 21 0 &nobias /* DE */ + &gpc 22 0 &nobias /* PS */ + &gpc 23 0 &nobias /* REV */ + &gpb 17 0 &nobias /* CLS */ + &gpb 18 0 &nobias>; /* SPL */ + }; + + pinfunc_lcd_nopins: pins-lcd-no-pins { + ingenic,pins = <>; + }; + }; + + pinfunc-nand { + pins_nand: pins-nand { + ingenic,pins = <&gpb 25 0 &nobias + &gpb 26 0 &nobias + &gpb 27 0 &nobias + &gpb 28 0 &nobias>; + }; + }; + + pinfunc-pwm0 { + pins_pwm0: pins-pwm0 { + ingenic,pins = <&gpd 23 0 &nobias>; + }; + }; + + pinfunc-pwm1 { + pins_pwm1: pins-pwm1 { + ingenic,pins = <&gpd 24 0 &nobias>; + }; + }; + + pinfunc-pwm2 { + pins_pwm2: pins-pwm2 { + ingenic,pins = <&gpd 25 0 &nobias>; + }; + }; + + pinfunc-pwm3 { + pins_pwm3: pins-pwm3 { + ingenic,pins = <&gpd 26 0 &nobias>; + }; + }; + + pinfunc-pwm4 { + pins_pwm4: pins-pwm4 { + ingenic,pins = <&gpd 27 0 &nobias>; + }; + }; + + pinfunc-pwm5 { + pins_pwm5: pins-pwm5 { + ingenic,pins = <&gpd 28 0 &nobias>; + }; + }; + + pinfunc-pwm6 { + pins_pwm6: pins-pwm6 { + ingenic,pins = <&gpd 30 0 &nobias>; + }; + }; + + pinfunc-pwm7 { + pins_pwm7: pins-pwm7 { + ingenic,pins = <&gpd 31 0 &nobias>; + }; + }; + }; + }; + uart0: serial@10030000 { compatible = "ingenic,jz4740-uart"; reg = <0x10030000 0x100>;