From patchwork Sat Jan 21 03:06:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9529749 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6D12E6046A for ; Sat, 21 Jan 2017 03:06:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 44445286D2 for ; Sat, 21 Jan 2017 03:06:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39789286E1; Sat, 21 Jan 2017 03:06:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBB5E286FB for ; Sat, 21 Jan 2017 03:06:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752550AbdAUDGq (ORCPT ); Fri, 20 Jan 2017 22:06:46 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:24863 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752639AbdAUDGp (ORCPT ); Fri, 20 Jan 2017 22:06:45 -0500 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 21 Jan 2017 12:06:42 +0900 Received: from relmlac3.idc.renesas.com (relmlac3.idc.renesas.com [10.200.69.23]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id A08DB43DF6; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: by relmlac3.idc.renesas.com (Postfix, from userid 0) id A3C7618070; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: from relmlac3.idc.renesas.com (localhost [127.0.0.1]) by relmlac3.idc.renesas.com (Postfix) with ESMTP id 9CFEC1806F; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac3.idc.renesas.com with ESMTP id NAB01315; Sat, 21 Jan 2017 12:06:42 +0900 X-IronPort-AV: E=Sophos;i="5.33,261,1477926000"; d="scan'208";a="232095763" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 21 Jan 2017 12:06:41 +0900 Received: from localhost.localdomain (unknown [143.103.58.132]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 97EC52F3; Sat, 21 Jan 2017 03:06:35 +0000 (UTC) From: Chris Brandt To: Ulf Hansson , Rob Herring , Mark Rutland , Simon Horman , Wolfram Sang , Geert Uytterhoeven Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v5 1/3] mmc: sh_mobile_sdhi: add support for 2 clocks Date: Fri, 20 Jan 2017 22:06:02 -0500 Message-Id: <20170121030604.7672-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170121030604.7672-1-chris.brandt@renesas.com> References: <20170121030604.7672-1-chris.brandt@renesas.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some controllers have 2 clock sources instead of 1. The 2nd clock is for the internal card detect logic and must be enabled/disabled along with the main core clock for proper operation. Signed-off-by: Chris Brandt Reviewed-by: Wolfram Sang --- v4: * add technical explanation within probe routine v3: * add more clarification to the commit log v2: * changed clk2 to clk_cd * disable clk if clk_cd enable fails * changed clock name from "carddetect" to "cd" --- drivers/mmc/host/sh_mobile_sdhi.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c index 59db14b..360d922 100644 --- a/drivers/mmc/host/sh_mobile_sdhi.c +++ b/drivers/mmc/host/sh_mobile_sdhi.c @@ -143,6 +143,7 @@ MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match); struct sh_mobile_sdhi { struct clk *clk; + struct clk *clk_cd; struct tmio_mmc_data mmc_data; struct tmio_mmc_dma dma_priv; struct pinctrl *pinctrl; @@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host) if (ret < 0) return ret; + ret = clk_prepare_enable(priv->clk_cd); + if (ret < 0) { + clk_disable_unprepare(priv->clk); + return ret; + } + /* * The clock driver may not know what maximum frequency * actually works, so it should be set with the max-frequency @@ -255,6 +262,8 @@ static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host) struct sh_mobile_sdhi *priv = host_to_priv(host); clk_disable_unprepare(priv->clk); + if (priv->clk_cd) + clk_disable_unprepare(priv->clk_cd); } static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc) @@ -572,6 +581,21 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev) goto eprobe; } + /* + * Some controllers provide a 2nd clock just to run the internal card + * detection logic. Unfortunately, the existing driver architecture does + * not support a separation of clocks for runtime PM usage. When + * native hotplug is used, the tmio driver assumes that the core + * must continue to run for card detect to stay active, so we cannot + * disable it. + * Additionally, it is prohibited to supply a clock to the core but not + * to the card detect circuit. That leaves us with if separate clocks + * are presented, we must treat them both as virtually 1 clock. + */ + priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); + if (IS_ERR(priv->clk_cd)) + priv->clk_cd = NULL; + priv->pinctrl = devm_pinctrl_get(&pdev->dev); if (!IS_ERR(priv->pinctrl)) { priv->pins_default = pinctrl_lookup_state(priv->pinctrl,