From patchwork Fri Mar 10 14:21:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ludovic Desroches X-Patchwork-Id: 9617489 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BD72D60414 for ; Fri, 10 Mar 2017 14:21:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7E29286EB for ; Fri, 10 Mar 2017 14:21:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BBED628725; Fri, 10 Mar 2017 14:21:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28ACC286EB for ; Fri, 10 Mar 2017 14:21:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933171AbdCJOVs (ORCPT ); Fri, 10 Mar 2017 09:21:48 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:43168 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933114AbdCJOVr (ORCPT ); Fri, 10 Mar 2017 09:21:47 -0500 Received: from ibiza.rfo.atmel.com (10.10.76.4) by chn-sv-exch04.mchp-main.com (10.10.76.105) with Microsoft SMTP Server id 14.3.181.6; Fri, 10 Mar 2017 07:21:44 -0700 From: Ludovic Desroches To: CC: , , Ludovic Desroches Subject: [RFC PATCH] mmc: core: HS DDR switch, don't change timing before checking status Date: Fri, 10 Mar 2017 15:21:17 +0100 Message-ID: <20170310142117.6060-1-ludovic.desroches@atmel.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <98664253-9a68-fa59-7f17-438b0d522fe8@microchip.com> References: <98664253-9a68-fa59-7f17-438b0d522fe8@microchip.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAC+NgFlrIKsWRWlGSWpSXmKPExsXCxeXDolu57VCEwey9m76zWRz5389o8WLtdVaL7ZsXMlscXxvuwOJx59oeNo87P5YyenzeJBfAHMWamZeUX5HAmvHmeT9bQTNPxd7HP9kbGI9ydjFycQgJrGaUuPF2G1MXIycHm4CpxKMFfcwgtoiAlETP02Ywm1mgWGLKx0lsILawQKREw79l7CA2i4CqROu1PrA4r4C9RMeHm2C2hICcRMP5+2C9nAKOEi+OXAabLyTgIPFv6maoekGJkzOfsEDMl5A4+OIFM0SNhsTr6VuZIOYESvSsXAplO0l0nZwINd9O4vD0i+wQtoPE9l1fWGBqdn2+zAxha0tsf7WPFcLWkdh2sB+qxlZiz4yJUDPdJR48Wg5l+0rMetgAVRMl0fjsIdMERolZSE6dheTUBYxMqxilnT38dIPDdF0jnD0MTPRykzMKdHMTM/P0kvNzNzFC4itzB2NbV8QhRkkOJiVR3rfNhyKE+JLyUyozEosz4otKc1KLDzHKcHAoSfBWbgHKCRalpqdWpGXmACMdJs3EwXmIUYKDR0mE9+JmoBre4oLE3OLMdIj8KUZJKXHeCpBmAZBERmkeXO8lRlEpYd6UZUA5noLUotzMEoj4LUZhjodMQix5+XmpUkB3MgCBBuMrRnEORiVh3i0gs3gy80rgdrwCWs8EtH4a30GQ9SWJCCmpBsb4msJNLVsSeOuCPn25ZPBPNsRi0zuVr7+SlFeHHO09UTbLTUA77QRffLvx72s5PT7Olr8SWF7ean3of2vtUXGRPyyLapLS+Opi96/l4WKp/V7KtSvt45czHwusrvlFef16erPMyOzYOR9LZp7fp2P4j7zaYFLZET219eK8qGV3pVR32K8uDFFiKc5INNRiLipOBAA0OM7TNAMAAA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ludovic Desroches The commit e173f8911f09 mmc: core: Update CMD13 polling policy when switch to HS DDR mode in addition to fix the management of CRC error, changes the place where the DDR52 timing is set. Before this commit, the sequence was: - set width to 8 with MMC_HS timing - send the switch command - check the status - set width to 8 with MMC_DDR52 timing - send the switch command - check the status Now: - set width to 8 with MMC_HS timing - send the switch command - set width to 8 with MMC_DDR52 timing - check the status It may lead to get an error when checking the status with some devices. Signed-off-by: Ludovic Desroches Tested-by: Nicolas Ferre --- drivers/mmc/core/mmc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 0fccca0..b837148 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1062,7 +1062,7 @@ static int mmc_select_hs_ddr(struct mmc_card *card) EXT_CSD_BUS_WIDTH, ext_csd_bits, card->ext_csd.generic_cmd6_time, - MMC_TIMING_MMC_DDR52, + 0, true, true, true); if (err) { pr_err("%s: switch to bus width %d ddr failed\n", @@ -1106,6 +1106,9 @@ static int mmc_select_hs_ddr(struct mmc_card *card) if (err) err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330); + if (!err) + mmc_set_timing(host, MMC_TIMING_MMC_DDR52); + return err; }