From patchwork Sun Aug 6 02:39:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9883479 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B73FA60392 for ; Sun, 6 Aug 2017 02:40:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A598928599 for ; Sun, 6 Aug 2017 02:40:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 99B68285B1; Sun, 6 Aug 2017 02:40:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 059DA285AD for ; Sun, 6 Aug 2017 02:40:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751223AbdHFCj5 (ORCPT ); Sat, 5 Aug 2017 22:39:57 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:45120 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751220AbdHFCj4 (ORCPT ); Sat, 5 Aug 2017 22:39:56 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id 1EA735FE5B; Sun, 6 Aug 2017 10:39:54 +0800 (CST) Date: Sun, 6 Aug 2017 10:39:54 +0800 From: Chen-Yu Tsai To: Icenowy Zheng Cc: Chen-Yu Tsai , Ulf Hansson , Maxime Ripard , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller Message-ID: <20170806023954.wwaredjwcm2p5pw7@wens.csie.org> References: <20170804213555.6024-1-icenowy@aosc.io> <20170804213555.6024-2-icenowy@aosc.io> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170804213555.6024-2-icenowy@aosc.io> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote: > The configuration struct of A64 EMMC(MMC2) compatible used to > have the needs_new_timings variable missing, which lead to NULL > pointer dereference now when trying to set up the old timings mode, as > the old timings mode doesn't exist at all on A64. I'm not familiar with the A64's eMMC controller. The datasheet says it does not have the timing switch register. It does not say whether it is always in the old or new timing mode. "needs_new_timings" probably meant that the switch has to be set. This fix doesn't really fix the underlying issue, which is the check for clk_delays was incorrectly replaced. sun4i/sun5i is also broken. Could you try this patch instead: <--- From 23b841a11294cb6a0cf1e146616b068f60c2ec7d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 6 Aug 2017 10:24:47 +0800 Subject: [PATCH] mmc: sunxi: Fix NULL pointer reference on clk_delays Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was replaced in commit b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings"). This patch adds back the check for clk_delays, and also adds comments for both checks in sunxi_mmc_clk_set_phase(). Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings") Signed-off-by: Chen-Yu Tsai --- drivers/mmc/host/sunxi-mmc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 3777517982dd..020547e5fa45 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -722,9 +722,14 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, { int index; + /* No need to set clk controller delays under new timings */ if (host->use_new_timings) return 0; + /* Some old controllers don't support delays */ + if (!host->cfg->clk_delays) + return 0; + /* determine delays */ if (rate <= 400000) { index = SDXC_CLK_400K;