From patchwork Wed Sep 27 20:56:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9974759 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6B44A60375 for ; Wed, 27 Sep 2017 20:57:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E94628F11 for ; Wed, 27 Sep 2017 20:57:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 538EB2935D; Wed, 27 Sep 2017 20:57:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0B5428F11 for ; Wed, 27 Sep 2017 20:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751911AbdI0U5F (ORCPT ); Wed, 27 Sep 2017 16:57:05 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:49598 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751969AbdI0U5B (ORCPT ); Wed, 27 Sep 2017 16:57:01 -0400 Received: by mail-pg0-f50.google.com with SMTP id m30so8428607pgn.6 for ; Wed, 27 Sep 2017 13:57:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xeFA31352wzENTz5KtIskwjiyIEqvnudevFw1GowxUk=; b=eaBTwIWbE2spknF9ENXEsUyzSkBJIOoMTE1dGcLC9a1p5mAKva+teuY4VjhNG3rXFa ZL8IEiT2g/blLUvB7zIlnZbg4Y/ZXJJUo0Vbd7misROhufvsudgG7KIDybgsoE7o/9In /unCvvv7Gz6gg6tuWmxGVbzAQpsyeEF7JkUZg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xeFA31352wzENTz5KtIskwjiyIEqvnudevFw1GowxUk=; b=pB5ITVsD+8ozyN7Op/1isqhBXUK2Iie4iQsUxsVUAN/nObMHdOct50Z09Qhqu8dXoP Hw7g4etf4X5h6BVarWYcAOtYYOaZMBJZI1VmUTrfro1gK/iJWXxrDql1dja+YgxNXYIm PujUymiqpiCApoEHM6CAN0tVtfMs5ZMPmp+wJrLR8oqZVjgnfH5V1kRi2RYbgL9qWRqL TlC2XqaEyhDA6y8R5bXZuQyvjY1lZAhOi7ZUnJKeQVICvZCV+z5Gc1Ad/GhgIS6PHaWm F/BStMFjm6s92+B3FYyU5qWW2+uUK1jJFfY+pKKPLe7WHtvLhkFmeT5W1wuZUPVcllI2 Le4w== X-Gm-Message-State: AHPjjUgNT8aJcxhvVE8zE4rXMCxu2hZNZIfUG1WjDMlCWYGuZogawdoG JdeW3GCku1bJKo8tJCA9FzoqhdKQ/tc= X-Google-Smtp-Source: AOwi7QCKz4kLFt/g8V2tg5VnQRMReGy/0OPupdiVK4mByjMdgQkiqLfKELo9rbhmPc/+/SO7HHFhgg== X-Received: by 10.99.110.199 with SMTP id j190mr2330671pgc.330.1506545821170; Wed, 27 Sep 2017 13:57:01 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.112.154]) by smtp.gmail.com with ESMTPSA id n12sm24666373pfb.131.2017.09.27.13.56.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 13:57:00 -0700 (PDT) From: Douglas Anderson To: jh80.chung@samsung.com, ulf.hansson@linaro.org, shawn.lin@rock-chips.com Cc: briannorris@chromium.org, amstan@chromium.org, xzy.xu@rock-chips.com, Douglas Anderson , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] mmc: dw_mmc: Fix the CTO timeout calculation Date: Wed, 27 Sep 2017 13:56:30 -0700 Message-Id: <20170927205631.31559-3-dianders@chromium.org> X-Mailer: git-send-email 2.14.2.822.g60be5d43e6-goog In-Reply-To: <20170927205631.31559-1-dianders@chromium.org> References: <20170927205631.31559-1-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In the commit 03de19212ea3 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme") we tried to calculate the expected hardware command timeout value. Unfortunately that calculation isn't quite correct in all cases. It used "bus_hz" but, as far as I can tell, it's supposed to use the card clock. Let's account for the div value, which is documented as 2x the value stored in the register, or 1 if the register is 0. NOTE: It's not expected that this will actually fix anything important since the 10 ms margin added by the function will pretty much dwarf any calculations. The card clock should be 100 kHz at minimum and: 1000 ms/s * (255 * 2) / 100000 Hz. Gives us 5.1 ms. ...so really the point of this patch is just to make the code more "correct" in case anyone ever tries to remove the 10 ms buffer. Fixes: 03de19212ea3 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme") Signed-off-by: Douglas Anderson Reviewed-by: Shawn Lin --- drivers/mmc/host/dw_mmc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index f5b2bb4b4d98..16516c528a88 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -401,10 +401,14 @@ static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) static inline void dw_mci_set_cto(struct dw_mci *host) { unsigned int cto_clks; + unsigned int cto_div; unsigned int cto_ms; cto_clks = mci_readl(host, TMOUT) & 0xff; - cto_ms = DIV_ROUND_UP(cto_clks, host->bus_hz / 1000); + cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; + if (cto_div == 0) + cto_div = 1; + cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz); /* add a bit spare time */ cto_ms += 10;