| Message ID | 20181031231340.1958-2-niklas.soderlund@ragnatech.se (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: renesas_sdhi: extend quirk selection to handle ES revisions | expand |
On Thu, Nov 01, 2018 at 12:13:38AM +0100, Niklas Söderlund wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Latest datasheet makes it clear that not all ES revisions of the H3 and > M3-W have the 4-tap HS400 mode quirk, currently the quirk is set > unconditionally for these two SoCs. Prepare to handle the quirk based on > SoC revision instead of compatibility value by using soc_device_match() > and set the TMIO_MMC_HAVE_4TAP_HS400 flag explicitly. > > The reason for adding a new quirks struct instead of just a flag is that > looking ahead it seems more quirks needs to be handled in a SoC revision > basis. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Hi Niklas, On Thu, Nov 1, 2018 at 12:15 AM Niklas Söderlund <niklas.soderlund@ragnatech.se> wrote: > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Latest datasheet makes it clear that not all ES revisions of the H3 and > M3-W have the 4-tap HS400 mode quirk, currently the quirk is set > unconditionally for these two SoCs. Prepare to handle the quirk based on > SoC revision instead of compatibility value by using soc_device_match() > and set the TMIO_MMC_HAVE_4TAP_HS400 flag explicitly. > > The reason for adding a new quirks struct instead of just a flag is that > looking ahead it seems more quirks needs to be handled in a SoC revision > basis. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! > @@ -602,11 +607,25 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) > renesas_sdhi_sdbuf_width(host, enable ? width : 16); > } > > +static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w = { I know this variable is renamed later, but sdhi_quirks_h3_m3w gives the impression it applies to all H3/M3-W variants. What about sdhi_quirks_4tap instead? > + .hs400_4taps = true, > +}; > + > +static const struct soc_device_attribute sdhi_quirks_match[] = { > + { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_h3_m3w }, > + { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_h3_m3w }, > + { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_h3_m3w }, > + { .soc_id = "r8a7796", .revision = "ES1.1", .data = &sdhi_quirks_h3_m3w }, > + { /* Sentinel. */ }, > +}; Gr{oetje,eeting}s, Geert
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index d3ac43c3d0b655dc..19d89b4dda64c13c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -32,6 +32,7 @@ #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinctrl-state.h> #include <linux/regulator/consumer.h> +#include <linux/sys_soc.h> #include "renesas_sdhi.h" #include "tmio_mmc.h" @@ -45,6 +46,10 @@ #define SDHI_VER_GEN3_SD 0xcc10 #define SDHI_VER_GEN3_SDMMC 0xcd10 +struct renesas_sdhi_quirks { + bool hs400_4taps; +}; + static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) { u32 val; @@ -602,11 +607,25 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) renesas_sdhi_sdbuf_width(host, enable ? width : 16); } +static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w = { + .hs400_4taps = true, +}; + +static const struct soc_device_attribute sdhi_quirks_match[] = { + { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_h3_m3w }, + { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_h3_m3w }, + { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_h3_m3w }, + { .soc_id = "r8a7796", .revision = "ES1.1", .data = &sdhi_quirks_h3_m3w }, + { /* Sentinel. */ }, +}; + int renesas_sdhi_probe(struct platform_device *pdev, const struct tmio_mmc_dma_ops *dma_ops) { struct tmio_mmc_data *mmd = pdev->dev.platform_data; + const struct renesas_sdhi_quirks *quirks = NULL; const struct renesas_sdhi_of_data *of_data; + const struct soc_device_attribute *attr; struct tmio_mmc_data *mmc_data; struct tmio_mmc_dma *dma_priv; struct tmio_mmc_host *host; @@ -616,6 +635,10 @@ int renesas_sdhi_probe(struct platform_device *pdev, of_data = of_device_get_match_data(&pdev->dev); + attr = soc_device_match(sdhi_quirks_match); + if (attr) + quirks = attr->data; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; @@ -681,6 +704,9 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->multi_io_quirk = renesas_sdhi_multi_io_quirk; host->dma_ops = dma_ops; + if (quirks && quirks->hs400_4taps) + mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400; + /* For some SoC, we disable internal WP. GPIO may override this */ if (mmc_can_gpio_ro(host->mmc)) mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;