From patchwork Thu Dec 6 15:18:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10716155 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FADB17DB for ; Thu, 6 Dec 2018 15:19:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D7F429AE5 for ; Thu, 6 Dec 2018 15:19:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 719C02E09E; Thu, 6 Dec 2018 15:19:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2285428A25 for ; Thu, 6 Dec 2018 15:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725908AbeLFPTB (ORCPT ); Thu, 6 Dec 2018 10:19:01 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40952 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726053AbeLFPSm (ORCPT ); Thu, 6 Dec 2018 10:18:42 -0500 Received: by mail-wm1-f65.google.com with SMTP id q26so1412765wmf.5 for ; Thu, 06 Dec 2018 07:18:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9D+IWNIkzvM4lr5AWVEe/1dPuYwCLo7SNBs7kvA6F/o=; b=V69wUMG28wtoJtdJvClt8+e4MNUFCgT9w5PW65OzLv56uK4D54BydOiREZ0QqqI6Yj nk587zOLB50DozkpeJgAVwuTXyfanIIiYzRWAk0+RmO0G77yvCTt1HQe0oF4D4U4gIX/ K+tH+Ei85fXP/cer2qzJ+E+nrrcsr/el3V1DRlWJ76S8dnjfpxCG1leb++zeQUGNt0sg 6XjfvIOLWDRXhd5mRCAZ1phYICvS+rKtgvMdf5InGSXVlZ4+w+CAg0FQjtIbn43RSCj6 QUOHKIBu5tWVUobolT9ZHj29k1SSP8jzn7rFngmbZFLolMiGJnzHhBVriKGiMENPrSFY Jnlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9D+IWNIkzvM4lr5AWVEe/1dPuYwCLo7SNBs7kvA6F/o=; b=fy/jJ1KYrQzvDtO2jFZg+Hoj1FF1zpEQGAAE3gCtoMNwJDdBpPpRc2UCrPvnXCsJyh skOphTQ2I2idfpVJFz6BwgSL4cVZR6ug5hZ+Joy5zQrd1JHRuFYeqUkgVCxdxVMabdEw EBbfDKE8ZmCTN7zM19J57Q/ZfbkV4ykkCZj/1ojTmsDZ/65fwC5ImSeEsvXBd4dV/U1d HQyjtIcvSqbGGA86KnJx6fAFqocSppIllY+a9ylscLGnyw/Fvtyj1zplZv08/WniMBir THOUorkOMDL2cBCrROUARgGGw6spaJfUv9a5vtw9Oh43Yyov/4TtUQpGPpffPp02O1mZ PUpA== X-Gm-Message-State: AA+aEWZSSTTKEY3SKpf5b3HP9rrEtCp9MHyRreDa57fAlNTRQxyno8NM LYwX6amO4ZDloK4ZxUfDKQD0Vg== X-Google-Smtp-Source: AFSGD/WZLKmAh/mxiuXK9Ct6fORvClnB6EooPxfPYwnm5i979312KWaCMeM6NJhlv80pX5rsGOOQTw== X-Received: by 2002:a1c:9d97:: with SMTP id g145mr20578555wme.152.1544109520556; Thu, 06 Dec 2018 07:18:40 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id j33sm939652wre.91.2018.12.06.07.18.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Dec 2018 07:18:40 -0800 (PST) From: Jerome Brunet To: Ulf Hansson , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFT PATCH 3/4] mmc: meson-gx: align default phase on soc vendor tree Date: Thu, 6 Dec 2018 16:18:27 +0100 Message-Id: <20181206151828.24417-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181206151828.24417-1-jbrunet@baylibre.com> References: <20181206151828.24417-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Align the default Core and Tx phase with the SoC vendor tree. Even if the Tx phase is different from what the documentation recommends, it seems to provide better results. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 5cc31e434ca1..837bed0b8c01 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -634,14 +634,8 @@ static int meson_mmc_clk_init(struct meson_host *host) if (ret) return ret; - /* - * Set phases : These values are mostly the datasheet recommended ones - * except for the Tx phase. Datasheet recommends 180 but some cards - * fail at initialisation with it. 270 works just fine, it fixes these - * initialisation issues and enable eMMC DDR52 mode. - */ clk_set_phase(host->mmc_clk, 180); - clk_set_phase(host->tx_clk, 270); + clk_set_phase(host->tx_clk, 0); clk_set_phase(host->rx_clk, 0); return clk_prepare_enable(host->mmc_clk);