| Message ID | 20191204071958.18553-1-chaotian.jing@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode | expand |
On Wed, Dec 4, 2019 at 3:20 PM Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > there is a chance that always get response CRC error after HS200 tuning, > the reason is that need set CMD_TA to 2. this modification is only for > MT8173. > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Tested-by: Hsin-Yi Wang <hsinyi@chromium.org> > ---
On Wed, 4 Dec 2019 at 08:20, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > there is a chance that always get response CRC error after HS200 tuning, > the reason is that need set CMD_TA to 2. this modification is only for > MT8173. > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> I have applied this for fixes, however it seems like this should also be tagged for stable, right? Is there a specific commit this fixes or should we just find the version it applies to? Kind regards Uffe > --- > drivers/mmc/host/mtk-sd.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 189e42674d85..010fe29a4888 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -228,6 +228,7 @@ > #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ > #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ > > +#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ > #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ > > #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ > @@ -1881,6 +1882,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) > > /* select EMMC50 PAD CMD tune */ > sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); > + sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); > > if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || > mmc->ios.timing == MMC_TIMING_UHS_SDR104) > -- > 2.18.0
On Tue, 2019-12-10 at 10:51 +0100, Ulf Hansson wrote: > On Wed, 4 Dec 2019 at 08:20, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > > > there is a chance that always get response CRC error after HS200 tuning, > > the reason is that need set CMD_TA to 2. this modification is only for > > MT8173. > > > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > > I have applied this for fixes, however it seems like this should also > be tagged for stable, right? > Yes! should be tagged for stable. > Is there a specific commit this fixes or should we just find the > version it applies to? > this patch should be a fix to commit: 1ede5cb88a29bba1aad1b68965c5fc8e00b20ed9 > Kind regards > Uffe > > > > > --- > > drivers/mmc/host/mtk-sd.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > > index 189e42674d85..010fe29a4888 100644 > > --- a/drivers/mmc/host/mtk-sd.c > > +++ b/drivers/mmc/host/mtk-sd.c > > @@ -228,6 +228,7 @@ > > #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ > > #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ > > > > +#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ > > #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ > > > > #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ > > @@ -1881,6 +1882,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) > > > > /* select EMMC50 PAD CMD tune */ > > sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); > > + sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); > > > > if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || > > mmc->ios.timing == MMC_TIMING_UHS_SDR104) > > -- > > 2.18.0 > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Tue, 10 Dec 2019 at 13:03, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > On Tue, 2019-12-10 at 10:51 +0100, Ulf Hansson wrote: > > On Wed, 4 Dec 2019 at 08:20, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > > > > > there is a chance that always get response CRC error after HS200 tuning, > > > the reason is that need set CMD_TA to 2. this modification is only for > > > MT8173. > > > > > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > > > > I have applied this for fixes, however it seems like this should also > > be tagged for stable, right? > > Yes! should be tagged for stable. > > Is there a specific commit this fixes or should we just find the > > version it applies to? > > > this patch should be a fix to commit: > 1ede5cb88a29bba1aad1b68965c5fc8e00b20ed9 Perfect, I add that! [...] Kind regards Uffe
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 189e42674d85..010fe29a4888 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -228,6 +228,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -1881,6 +1882,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) /* select EMMC50 PAD CMD tune */ sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); + sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || mmc->ios.timing == MMC_TIMING_UHS_SDR104)
there is a chance that always get response CRC error after HS200 tuning, the reason is that need set CMD_TA to 2. this modification is only for MT8173. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 2 ++ 1 file changed, 2 insertions(+)