| Message ID | 20200128090636.13689-6-ludovic.barre@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: mmci: sdmmc: add sdr104 support | expand |
On Tue, 28 Jan 2020 10:06:32 +0100, Ludovic Barre wrote: > To support the sdr104 mode, the sdmmc variant has a > hardware delay block to manage the clock phase when sampling > data received by the card. > > This patch adds a second base register (optional) for > sdmmc delay block. > > Signed-off-by: Ludovic Barre <ludovic.barre@st.com> > --- > Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt index 6d3c626e017d..4ec921e4bf34 100644 --- a/Documentation/devicetree/bindings/mmc/mmci.txt +++ b/Documentation/devicetree/bindings/mmc/mmci.txt @@ -28,6 +28,8 @@ specific for ux500 variant: - st,sig-pin-fbclk : feedback clock signal pin used. specific for sdmmc variant: +- reg : a second base register may be defined if a delay + block is present and used for tuning. - st,sig-dir : signal direction polarity used for cmd, dat0 dat123. - st,neg-edge : data & command phase relation, generated on sd clock falling edge.
To support the sdr104 mode, the sdmmc variant has a hardware delay block to manage the clock phase when sampling data received by the card. This patch adds a second base register (optional) for sdmmc delay block. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> --- Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ 1 file changed, 2 insertions(+)