From patchwork Wed Aug 26 08:41:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11737599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B72C722 for ; Wed, 26 Aug 2020 08:41:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B73320707 for ; Wed, 26 Aug 2020 08:41:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="b5fx/8JM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727793AbgHZIl2 (ORCPT ); Wed, 26 Aug 2020 04:41:28 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:45764 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727792AbgHZIlZ (ORCPT ); Wed, 26 Aug 2020 04:41:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1598431284; x=1629967284; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8mdaeBmcxu3o47l7H/D8BVFS4SLTi4OP6sCmaG9VR4A=; b=b5fx/8JM97ZR9uOK7trTU2O41G+f2Q17XgeveHlrzsuGnbK7wDD6q7U7 /kIUGOrD8rtkOzS5xRkNtanAJrMlAKVXBQGFVWMjWGZ5vFUn483HbjGyl yk808jEEHkqrKp9kz3AaSuim59VfE+S/jZa6gVyP0KgutMEJ42OkC3oiJ KW9N/30nX4NcezMlIAN+6ULZa2D3Uc0v7/NqdOzXIsgermV5l3iaZ5uJZ /rtoDKImlMuOilIC2t8ou+hB5NNUtMpwXdbaREsxXjjnYVNzTNIABlJYk itt0NcFS778M3XxHVIyQL14ZxPkOL/D8srX/viWnVnAfCIbEj1fV4S4bw g==; IronPort-SDR: WIDO+QrcQqlAsFQOW4uG6PkiwAXG52D435peGfA8HicTtoO+67hxVzEwIvvUdjsOQ+59h2utb6 DxUQJK9BZ3sTGcKDJRyBzD0FQQMHBA+BJykzsPN9zLshRc8MrbsyrvTN1RhUbr5/tzT7Nm8xV7 rxmAniXYITtmYA5uns6NU8yRYWbUPk/LZNeg2VNB8Am6ckwV0P4NaOuq3eS4+FxIecAuEvHCpP a63dc17L6GDCeoXTRwHmDIgwrw7uoWTEWIcbYPqHo11FEkJ6yGxegcKE+VftnkNiRJBFdMnmbs OiE= X-IronPort-AV: E=Sophos;i="5.76,355,1592895600"; d="scan'208";a="89395762" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2020 01:41:24 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 26 Aug 2020 01:41:23 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 26 Aug 2020 01:41:21 -0700 From: Lars Povlsen To: Rob Herring CC: Lars Povlsen , Ulf Hansson , Adrian Hunter , "Microchip Linux Driver Support" , , , , Alexandre Belloni Subject: [PATCH v6] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Date: Wed, 26 Aug 2020 10:41:07 +0200 Message-ID: <20200826084107.20185-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The Sparx5 SDHCI controller is based on the Designware controller IP. Signed-off-by: Lars Povlsen --- Note: This patch is now separated from original patch series. v6 changes: - Change "mmc0@600800000" => "mmc@600800000" [from earlier patch series, only applicable changes] Changes in v5: - Change (mmc|sdhci)@600800000 to mmc0@600800000 Changes in v4: n/a Changes in v3: - Add dt-bindings for property "microchip,clock-delay" Changes in v2: n/a .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml -- 2.27.0 diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml new file mode 100644 index 000000000000..55883290543b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Mobile Storage Host Controller Binding + +allOf: + - $ref: "mmc-controller.yaml" + +maintainers: + - Lars Povlsen + +# Everything else is described in the common file +properties: + compatible: + const: microchip,dw-sparx5-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Handle to "core" clock for the sdhci controller. + + clock-names: + items: + - const: core + + microchip,clock-delay: + description: Delay clock to card to meet setup time requirements. + Each step increase by 1.25ns. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 15 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + sdhci0: mmc@600800000 { + compatible = "microchip,dw-sparx5-sdhci"; + reg = <0x00800000 0x1000>; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + clocks = <&clks CLK_ID_AUX1>; + clock-names = "core"; + assigned-clocks = <&clks CLK_ID_AUX1>; + assigned-clock-rates = <800000000>; + interrupts = ; + bus-width = <8>; + microchip,clock-delay = <10>; + };