From patchwork Tue Sep 15 06:11:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11775629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 156D96CA for ; Tue, 15 Sep 2020 06:13:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E29CA214F1 for ; Tue, 15 Sep 2020 06:13:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iArR4DRX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726235AbgIOGNo (ORCPT ); Tue, 15 Sep 2020 02:13:44 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:21793 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726198AbgIOGN1 (ORCPT ); Tue, 15 Sep 2020 02:13:27 -0400 X-UUID: 61ed0938819e4c93ba98968d9b663810-20200915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=XLnueKG77zqgGlKTvOF9hBmcnot7DeiZK4sccS5sVaQ=; b=iArR4DRX2NGk8hjLmvgJS2foaEw8LHLUScw723dW1VhaszHVMZVeoG1r+7QAtUDSMWIKFJ5BVMKY9Kd6sxsFlsFC+1YRXhm7L76maxJFJea5+sHWOuZdtQ9UBpg/zUOhncjk0MC281MN6fNwlJtd/9Jpb0Gin8mz6oh8EuqUx10=; X-UUID: 61ed0938819e4c93ba98968d9b663810-20200915 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 109680203; Tue, 15 Sep 2020 14:13:23 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Sep 2020 14:13:21 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Sep 2020 14:13:21 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [RESEND 3/3] mmc: mediatek: Add subsys clock control for MT8192 msdc Date: Tue, 15 Sep 2020 14:11:10 +0800 Message-ID: <20200915061110.25833-4-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200915061110.25833-1-wenbin.mei@mediatek.com> References: <20200915061110.25833-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org MT8192 msdc is an independent sub system, we need control more bus clocks for it. Add support for the additional subsys clocks to allow it to be configured appropriately. Signed-off-by: Wenbin Mei --- drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++--------- 1 file changed, 59 insertions(+), 18 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index ed2b24691b4f..f311192c8d05 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -426,6 +426,8 @@ struct msdc_host { struct clk *h_clk; /* msdc h_clk */ struct clk *bus_clk; /* bus clock which used to access register */ struct clk *src_clk_cg; /* msdc source clock control gate */ + struct clk *sys_clk_cg; /* msdc subsys clock control gate */ + struct clk_bulk_data bulk_clks[3]; /* pclk, axi, ahb clock control gate */ u32 mclk; /* mmc subsystem clock frequency */ u32 src_clk_freq; /* source clock frequency */ unsigned char timing; @@ -784,6 +786,8 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) static void msdc_gate_clock(struct msdc_host *host) { + clk_bulk_disable_unprepare(ARRAY_SIZE(host->bulk_clks), + host->bulk_clks); clk_disable_unprepare(host->src_clk_cg); clk_disable_unprepare(host->src_clk); clk_disable_unprepare(host->bus_clk); @@ -792,10 +796,17 @@ static void msdc_gate_clock(struct msdc_host *host) static void msdc_ungate_clock(struct msdc_host *host) { + int ret; + clk_prepare_enable(host->h_clk); clk_prepare_enable(host->bus_clk); clk_prepare_enable(host->src_clk); clk_prepare_enable(host->src_clk_cg); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(host->bulk_clks), + host->bulk_clks); + if (ret) + dev_dbg(host->dev, "enable clks failed!\n"); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) cpu_relax(); } @@ -2361,6 +2372,52 @@ static void msdc_of_property_parse(struct platform_device *pdev, host->cqhci = false; } +static int msdc_of_clock_parse(struct platform_device *pdev, + struct msdc_host *host) +{ + struct clk *clk; + + host->src_clk = devm_clk_get(&pdev->dev, "source"); + if (IS_ERR(host->src_clk)) + return PTR_ERR(host->src_clk); + + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(host->h_clk)) + return PTR_ERR(host->h_clk); + + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(host->bus_clk)) + host->bus_clk = NULL; + + /*source clock control gate is optional clock*/ + host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); + if (IS_ERR(host->src_clk_cg)) + host->src_clk_cg = NULL; + + host->sys_clk_cg = devm_clk_get(&pdev->dev, "sys_cg"); + if (IS_ERR(host->sys_clk_cg)) + host->sys_clk_cg = NULL; + else + clk_prepare_enable(host->sys_clk_cg); + + clk = devm_clk_get(&pdev->dev, "pclk_cg"); + if (IS_ERR(clk)) + clk = NULL; + host->bulk_clks[0].clk = clk; + + clk = devm_clk_get(&pdev->dev, "axi_cg"); + if (IS_ERR(clk)) + clk = NULL; + host->bulk_clks[1].clk = clk; + + clk = devm_clk_get(&pdev->dev, "ahb_cg"); + if (IS_ERR(clk)) + clk = NULL; + host->bulk_clks[2].clk = clk; + + return 0; +} + static int msdc_drv_probe(struct platform_device *pdev) { struct mmc_host *mmc; @@ -2400,25 +2457,9 @@ static int msdc_drv_probe(struct platform_device *pdev) if (ret) goto host_free; - host->src_clk = devm_clk_get(&pdev->dev, "source"); - if (IS_ERR(host->src_clk)) { - ret = PTR_ERR(host->src_clk); - goto host_free; - } - - host->h_clk = devm_clk_get(&pdev->dev, "hclk"); - if (IS_ERR(host->h_clk)) { - ret = PTR_ERR(host->h_clk); + ret = msdc_of_clock_parse(pdev, host); + if (ret) goto host_free; - } - - host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); - if (IS_ERR(host->bus_clk)) - host->bus_clk = NULL; - /*source clock control gate is optional clock*/ - host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); - if (IS_ERR(host->src_clk_cg)) - host->src_clk_cg = NULL; host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "hrst");