diff mbox series

[6/6] mmc: sdhci_am654: Enable tuning for SDR50

Message ID 20200923105206.7988-7-faiz_abbas@ti.com (mailing list archive)
State New, archived
Headers show
Series Add UHS mode support for TI's AM65x, J721e, J7200 boards | expand

Commit Message

Faiz Abbas Sept. 23, 2020, 10:52 a.m. UTC 
According to the SW tuning App note[1], tuning is required for all
UHS speed modes. Tuning for SDR50 is not enabled in Capabilities by
default so enable it from the CTL_CFG registers.

[1] https://www.ti.com/lit/pdf/spract9

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
 drivers/mmc/host/sdhci_am654.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 5af7638ad606..2bce962bf7e4 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -19,9 +19,11 @@ 
 
 /* CTL_CFG Registers */
 #define CTL_CFG_2		0x14
+#define CTL_CFG_3		0x18
 
 #define SLOTTYPE_MASK		GENMASK(31, 30)
 #define SLOTTYPE_EMBEDDED	BIT(30)
+#define TUNINGFORSDR50_MASK	BIT(13)
 
 /* PHY Registers */
 #define PHY_CTRL1	0x100
@@ -646,6 +648,10 @@  static int sdhci_am654_init(struct sdhci_host *host)
 	regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
 			   ctl_cfg_2);
 
+	/* Enable tuning for SDR50 */
+	regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
+			   TUNINGFORSDR50_MASK);
+
 	ret = sdhci_setup_host(host);
 	if (ret)
 		return ret;