| Message ID | 20201123063004.337345-4-andrew@aj.id.au (mailing list archive) |
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Mon, 23 Nov 2020 01:30:45 -0500 (EST)
From: Andrew Jeffery <andrew@aj.id.au>
To: linux-mmc@vger.kernel.org
Cc: robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com,
ulf.hansson@linaro.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
ryan_chen@aspeedtech.com
Subject: [PATCH v3 3/3] ARM: dts: rainier: Add eMMC clock phase compensation
Date: Mon, 23 Nov 2020 17:00:04 +1030
Message-Id: <20201123063004.337345-4-andrew@aj.id.au>
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|
| Series |
mmc: sdhci-of-aspeed: Expose phase delay tuning
|
expand
|
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 21ae880c7530..ab8d37d49f30 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -186,6 +186,7 @@ &pinctrl_emmc_default { &emmc { status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; }; &fsim0 {
Determined by scope measurements at speed. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 + 1 file changed, 1 insertion(+)