| Message ID | 20210817090313.31858-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Document RZ/G2L SDHI controller bindings | expand |
On Tue, 17 Aug 2021 10:03:13 +0100, Biju Das wrote: > Document RZ/G2L SDHI controller bindings. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v3->v4: > * Defined clock-names for RZ/G2L SoC and make it as a required property > v2->v3: > * split the patch into 2, first one for fixing dtbs-check issue and > later one for documenting RZ/G2L SDHI bindings. > v1->v2: > * Fixed dtbs-check issue for RZ/A{1,2} platforms. > --- > .../devicetree/bindings/mmc/renesas,sdhi.yaml | 73 +++++++++++++------ > 1 file changed, 52 insertions(+), 21 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Tue, 17 Aug 2021 at 11:03, Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Document RZ/G2L SDHI controller bindings. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Applied for next, thanks! Kind regards Uffe > --- > v3->v4: > * Defined clock-names for RZ/G2L SoC and make it as a required property > v2->v3: > * split the patch into 2, first one for fixing dtbs-check issue and > later one for documenting RZ/G2L SDHI bindings. > v1->v2: > * Fixed dtbs-check issue for RZ/A{1,2} platforms. > --- > .../devicetree/bindings/mmc/renesas,sdhi.yaml | 73 +++++++++++++------ > 1 file changed, 52 insertions(+), 21 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > index 43584f4f4c7e..9f1e7092cf44 100644 > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > @@ -44,19 +44,20 @@ properties: > - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) > - items: > - enum: > - - renesas,sdhi-r8a774a1 # RZ/G2M > - - renesas,sdhi-r8a774b1 # RZ/G2N > - - renesas,sdhi-r8a774c0 # RZ/G2E > - - renesas,sdhi-r8a774e1 # RZ/G2H > - - renesas,sdhi-r8a7795 # R-Car H3 > - - renesas,sdhi-r8a7796 # R-Car M3-W > - - renesas,sdhi-r8a77961 # R-Car M3-W+ > - - renesas,sdhi-r8a77965 # R-Car M3-N > - - renesas,sdhi-r8a77970 # R-Car V3M > - - renesas,sdhi-r8a77980 # R-Car V3H > - - renesas,sdhi-r8a77990 # R-Car E3 > - - renesas,sdhi-r8a77995 # R-Car D3 > - - renesas,sdhi-r8a779a0 # R-Car V3U > + - renesas,sdhi-r8a774a1 # RZ/G2M > + - renesas,sdhi-r8a774b1 # RZ/G2N > + - renesas,sdhi-r8a774c0 # RZ/G2E > + - renesas,sdhi-r8a774e1 # RZ/G2H > + - renesas,sdhi-r8a7795 # R-Car H3 > + - renesas,sdhi-r8a7796 # R-Car M3-W > + - renesas,sdhi-r8a77961 # R-Car M3-W+ > + - renesas,sdhi-r8a77965 # R-Car M3-N > + - renesas,sdhi-r8a77970 # R-Car V3M > + - renesas,sdhi-r8a77980 # R-Car V3H > + - renesas,sdhi-r8a77990 # R-Car E3 > + - renesas,sdhi-r8a77995 # R-Car D3 > + - renesas,sdhi-r8a779a0 # R-Car V3U > + - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} > - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 > > reg: > @@ -66,15 +67,9 @@ properties: > minItems: 1 > maxItems: 3 > > - clocks: > - minItems: 1 > - maxItems: 2 > + clocks: true > > - clock-names: > - minItems: 1 > - items: > - - const: core > - - const: cd > + clock-names: true > > dmas: > minItems: 4 > @@ -108,6 +103,42 @@ properties: > allOf: > - $ref: "mmc-controller.yaml" > > + - if: > + properties: > + compatible: > + contains: > + const: renesas,sdhi-r9a07g044 > + then: > + properties: > + clocks: > + items: > + - description: IMCLK, SDHI channel main clock1. > + - description: IMCLK2, SDHI channel main clock2. When this clock is > + turned off, external SD card detection cannot be > + detected. > + - description: CLK_HS, SDHI channel High speed clock which operates > + 4 times that of SDHI channel main clock1. > + - description: ACLK, SDHI channel bus clock. > + clock-names: > + items: > + - const: imclk > + - const: imclk2 > + - const: clk_hs > + - const: aclk > + required: > + - clock-names > + - resets > + else: > + properties: > + clocks: > + minItems: 1 > + maxItems: 2 > + clock-names: > + minItems: 1 > + items: > + - const: core > + - const: cd > + > - if: > properties: > compatible: > -- > 2.17.1 >
Hi Biju, On Tue, Aug 17, 2021 at 11:03 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Document RZ/G2L SDHI controller bindings. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch, which is now commit bfadee4554c3782b ("dt-bindings: mmc: renesas,sdhi: Document RZ/G2L bindings") in v5.15. > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > @@ -44,19 +44,20 @@ properties: > - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) > - items: > - enum: > - - renesas,sdhi-r8a774a1 # RZ/G2M > - - renesas,sdhi-r8a774b1 # RZ/G2N > - - renesas,sdhi-r8a774c0 # RZ/G2E > - - renesas,sdhi-r8a774e1 # RZ/G2H > - - renesas,sdhi-r8a7795 # R-Car H3 > - - renesas,sdhi-r8a7796 # R-Car M3-W > - - renesas,sdhi-r8a77961 # R-Car M3-W+ > - - renesas,sdhi-r8a77965 # R-Car M3-N > - - renesas,sdhi-r8a77970 # R-Car V3M > - - renesas,sdhi-r8a77980 # R-Car V3H > - - renesas,sdhi-r8a77990 # R-Car E3 > - - renesas,sdhi-r8a77995 # R-Car D3 > - - renesas,sdhi-r8a779a0 # R-Car V3U > + - renesas,sdhi-r8a774a1 # RZ/G2M > + - renesas,sdhi-r8a774b1 # RZ/G2N > + - renesas,sdhi-r8a774c0 # RZ/G2E > + - renesas,sdhi-r8a774e1 # RZ/G2H > + - renesas,sdhi-r8a7795 # R-Car H3 > + - renesas,sdhi-r8a7796 # R-Car M3-W > + - renesas,sdhi-r8a77961 # R-Car M3-W+ > + - renesas,sdhi-r8a77965 # R-Car M3-N > + - renesas,sdhi-r8a77970 # R-Car V3M > + - renesas,sdhi-r8a77980 # R-Car V3H > + - renesas,sdhi-r8a77990 # R-Car E3 > + - renesas,sdhi-r8a77995 # R-Car D3 > + - renesas,sdhi-r8a779a0 # R-Car V3U > + - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} > - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 I don't think SDHI on RZ/G2L is fully compatible with SDHI on R-Car Gen3... > > reg: > @@ -66,15 +67,9 @@ properties: > minItems: 1 > maxItems: 3 > > - clocks: > - minItems: 1 > - maxItems: 2 > + clocks: true > > - clock-names: > - minItems: 1 > - items: > - - const: core > - - const: cd > + clock-names: true > > dmas: > minItems: 4 > @@ -108,6 +103,42 @@ properties: > allOf: > - $ref: "mmc-controller.yaml" > > + - if: > + properties: > + compatible: > + contains: > + const: renesas,sdhi-r9a07g044 > + then: > + properties: > + clocks: > + items: > + - description: IMCLK, SDHI channel main clock1. > + - description: IMCLK2, SDHI channel main clock2. When this clock is > + turned off, external SD card detection cannot be > + detected. > + - description: CLK_HS, SDHI channel High speed clock which operates > + 4 times that of SDHI channel main clock1. > + - description: ACLK, SDHI channel bus clock. > + clock-names: > + items: > + - const: imclk > + - const: imclk2 > + - const: clk_hs > + - const: aclk > + required: > + - clock-names > + - resets > + else: > + properties: > + clocks: > + minItems: 1 > + maxItems: 2 > + clock-names: > + minItems: 1 > + items: > + - const: core > + - const: cd > + > - if: > properties: > compatible: ... as the clock handling is completely different. Does this actually work with the current Linux SDHI driver? How are the extra clocks handled? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, > Subject: Re: [PATCH v4 2/2] dt-bindings: mmc: renesas,sdhi: Document > RZ/G2L bindings > > Hi Biju, > > On Tue, Aug 17, 2021 at 11:03 AM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Document RZ/G2L SDHI controller bindings. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch, which is now commit bfadee4554c3782b > ("dt-bindings: mmc: renesas,sdhi: Document RZ/G2L bindings") in v5.15. > > > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > > @@ -44,19 +44,20 @@ properties: > > - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) > > - items: > > - enum: > > - - renesas,sdhi-r8a774a1 # RZ/G2M > > - - renesas,sdhi-r8a774b1 # RZ/G2N > > - - renesas,sdhi-r8a774c0 # RZ/G2E > > - - renesas,sdhi-r8a774e1 # RZ/G2H > > - - renesas,sdhi-r8a7795 # R-Car H3 > > - - renesas,sdhi-r8a7796 # R-Car M3-W > > - - renesas,sdhi-r8a77961 # R-Car M3-W+ > > - - renesas,sdhi-r8a77965 # R-Car M3-N > > - - renesas,sdhi-r8a77970 # R-Car V3M > > - - renesas,sdhi-r8a77980 # R-Car V3H > > - - renesas,sdhi-r8a77990 # R-Car E3 > > - - renesas,sdhi-r8a77995 # R-Car D3 > > - - renesas,sdhi-r8a779a0 # R-Car V3U > > + - renesas,sdhi-r8a774a1 # RZ/G2M > > + - renesas,sdhi-r8a774b1 # RZ/G2N > > + - renesas,sdhi-r8a774c0 # RZ/G2E > > + - renesas,sdhi-r8a774e1 # RZ/G2H > > + - renesas,sdhi-r8a7795 # R-Car H3 > > + - renesas,sdhi-r8a7796 # R-Car M3-W > > + - renesas,sdhi-r8a77961 # R-Car M3-W+ > > + - renesas,sdhi-r8a77965 # R-Car M3-N > > + - renesas,sdhi-r8a77970 # R-Car V3M > > + - renesas,sdhi-r8a77980 # R-Car V3H > > + - renesas,sdhi-r8a77990 # R-Car E3 > > + - renesas,sdhi-r8a77995 # R-Car D3 > > + - renesas,sdhi-r8a779a0 # R-Car V3U > > + - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} > > - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 > > I don't think SDHI on RZ/G2L is fully compatible with SDHI on R-Car > Gen3... It is is same IP, it has 2 main clk(core clocks), 1 high speed clock and 1 bus clock. Core clocks are same running at 133MHz, High speed clock is at 533 MHz(133 x4) and bus clock At 200MHz. > > > > > reg: > > @@ -66,15 +67,9 @@ properties: > > minItems: 1 > > maxItems: 3 > > > > - clocks: > > - minItems: 1 > > - maxItems: 2 > > + clocks: true > > > > - clock-names: > > - minItems: 1 > > - items: > > - - const: core > > - - const: cd > > + clock-names: true > > > > dmas: > > minItems: 4 > > @@ -108,6 +103,42 @@ properties: > > allOf: > > - $ref: "mmc-controller.yaml" > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: renesas,sdhi-r9a07g044 > > + then: > > + properties: > > + clocks: > > + items: > > + - description: IMCLK, SDHI channel main clock1. > > + - description: IMCLK2, SDHI channel main clock2. When this > clock is > > + turned off, external SD card detection > cannot be > > + detected. > > + - description: CLK_HS, SDHI channel High speed clock which > operates > > + 4 times that of SDHI channel main clock1. > > + - description: ACLK, SDHI channel bus clock. > > + clock-names: > > + items: > > + - const: imclk > > + - const: imclk2 > > + - const: clk_hs > > + - const: aclk > > + required: > > + - clock-names > > + - resets > > + else: > > + properties: > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + clock-names: > > + minItems: 1 > > + items: > > + - const: core > > + - const: cd > > + > > - if: > > properties: > > compatible: > > ... as the clock handling is completely different. > > Does this actually work with the current Linux SDHI driver? How are the > extra clocks handled? Yes, it works. Extra clocks are by PM framework. We added mutli-clock handling[1] in clock PM. [1]:- https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/renesas/rzg2l-cpg.c?h=v5.15#n585 First clock is core-clk[2], so it gets rate. [2]https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.15#n906 I need to apply the latest patch series from Wolfram to check, the introduction of SDH clock breaks anything on RZ/G2L. Regards, biju > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
Hi everyone, > > + - description: IMCLK, SDHI channel main clock1. Sounds like "core" > > + - description: IMCLK2, SDHI channel main clock2. When this clock is > > + turned off, external SD card detection cannot be > > + detected. "cd" > > + - description: CLK_HS, SDHI channel High speed clock which operates > > + 4 times that of SDHI channel main clock1. "clkh" compared to the Gen3 bindings to me. > > + - description: ACLK, SDHI channel bus clock. This I don't understand. The CPG-MSSR clock? > Does this actually work with the current Linux SDHI driver? How are > the extra clocks handled? It may work out of the box if their HW can have "clkh" enabled all the time and this is their default. Gen3 has recommendations to disable clkh for slow transfer modes, so we need handling of clkh Kind regards, Wolfram
Hi Wolfram, On Fri, Nov 12, 2021 at 12:56 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > > + - description: IMCLK, SDHI channel main clock1. > > Sounds like "core" > > > > + - description: IMCLK2, SDHI channel main clock2. When this clock is > > > + turned off, external SD card detection cannot be > > > + detected. > > "cd" > > > > + - description: CLK_HS, SDHI channel High speed clock which operates > > > + 4 times that of SDHI channel main clock1. > > "clkh" compared to the Gen3 bindings to me. > > > > + - description: ACLK, SDHI channel bus clock. > > This I don't understand. The CPG-MSSR clock? RZ/G2L has more fine-grained control of module clocks. On e.g. R-Car SoCs, there is a single "MSTP" bit to disable "the" module clock, but in practice it may control multiple clock inputs to a module. The actual clock tree is not documented, so we model this as a single module clock. So probably the MSTP bit controls both the main channel clock and the bus clock. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 43584f4f4c7e..9f1e7092cf44 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -44,19 +44,20 @@ properties: - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) - items: - enum: - - renesas,sdhi-r8a774a1 # RZ/G2M - - renesas,sdhi-r8a774b1 # RZ/G2N - - renesas,sdhi-r8a774c0 # RZ/G2E - - renesas,sdhi-r8a774e1 # RZ/G2H - - renesas,sdhi-r8a7795 # R-Car H3 - - renesas,sdhi-r8a7796 # R-Car M3-W - - renesas,sdhi-r8a77961 # R-Car M3-W+ - - renesas,sdhi-r8a77965 # R-Car M3-N - - renesas,sdhi-r8a77970 # R-Car V3M - - renesas,sdhi-r8a77980 # R-Car V3H - - renesas,sdhi-r8a77990 # R-Car E3 - - renesas,sdhi-r8a77995 # R-Car D3 - - renesas,sdhi-r8a779a0 # R-Car V3U + - renesas,sdhi-r8a774a1 # RZ/G2M + - renesas,sdhi-r8a774b1 # RZ/G2N + - renesas,sdhi-r8a774c0 # RZ/G2E + - renesas,sdhi-r8a774e1 # RZ/G2H + - renesas,sdhi-r8a7795 # R-Car H3 + - renesas,sdhi-r8a7796 # R-Car M3-W + - renesas,sdhi-r8a77961 # R-Car M3-W+ + - renesas,sdhi-r8a77965 # R-Car M3-N + - renesas,sdhi-r8a77970 # R-Car V3M + - renesas,sdhi-r8a77980 # R-Car V3H + - renesas,sdhi-r8a77990 # R-Car E3 + - renesas,sdhi-r8a77995 # R-Car D3 + - renesas,sdhi-r8a779a0 # R-Car V3U + - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 reg: @@ -66,15 +67,9 @@ properties: minItems: 1 maxItems: 3 - clocks: - minItems: 1 - maxItems: 2 + clocks: true - clock-names: - minItems: 1 - items: - - const: core - - const: cd + clock-names: true dmas: minItems: 4 @@ -108,6 +103,42 @@ properties: allOf: - $ref: "mmc-controller.yaml" + - if: + properties: + compatible: + contains: + const: renesas,sdhi-r9a07g044 + then: + properties: + clocks: + items: + - description: IMCLK, SDHI channel main clock1. + - description: IMCLK2, SDHI channel main clock2. When this clock is + turned off, external SD card detection cannot be + detected. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. + - description: ACLK, SDHI channel bus clock. + clock-names: + items: + - const: imclk + - const: imclk2 + - const: clk_hs + - const: aclk + required: + - clock-names + - resets + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd + - if: properties: compatible: