| Message ID | 20211110191610.5664-2-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk/mmc: renesas_sdhi: refactor SDnH to be a separate clock | expand |
CC clk On Wed, Nov 10, 2021 at 8:16 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Currently, SDnH is handled together with SDn. This caused lots of > problems, so we want SDnH as a separate clock. Introduce a dummy SDnH > type here which creates a fixed-factor clock with factor 1. That allows > us to convert the per-SoC CPG drivers while keeping the old behaviour > for now. A later patch then will add the proper functionality. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > > Changes since RFC v1: > * fixed typo in commit message > * added tag from Geert > > drivers/clk/renesas/rcar-cpg-lib.c | 9 +++++++++ > drivers/clk/renesas/rcar-cpg-lib.h | 4 ++++ > drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++ > drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ > 4 files changed, 21 insertions(+) > > diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c > index 5678768ee1f2..351cb9c04f5c 100644 > --- a/drivers/clk/renesas/rcar-cpg-lib.c > +++ b/drivers/clk/renesas/rcar-cpg-lib.c > @@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, > /* > * SDn Clock > */ > + > +struct clk * __init cpg_sdh_clk_register(const char *name, > + void __iomem *sdnckcr, const char *parent_name, > + struct raw_notifier_head *notifiers) > +{ > + /* placeholder during transition */ > + return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1); > +} > + > #define CPG_SD_STP_HCK BIT(9) > #define CPG_SD_STP_CK BIT(8) > > diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h > index d00c91b116ca..548cb9562f35 100644 > --- a/drivers/clk/renesas/rcar-cpg-lib.h > +++ b/drivers/clk/renesas/rcar-cpg-lib.h > @@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, > > void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set); > > +struct clk * __init cpg_sdh_clk_register(const char *name, > + void __iomem *sdnckcr, const char *parent_name, > + struct raw_notifier_head *notifiers); > + > struct clk * __init cpg_sd_clk_register(const char *name, > void __iomem *base, unsigned int offset, const char *parent_name, > struct raw_notifier_head *notifiers, bool skip_first); > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index 558191c99b48..182b189bc8f4 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -486,6 +486,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, > mult *= 2; > break; > > + case CLK_TYPE_GEN3_SDH: > + return cpg_sdh_clk_register(core->name, base + core->offset, > + __clk_get_name(parent), notifiers); > + > case CLK_TYPE_GEN3_SD: > return cpg_sd_clk_register(core->name, base, core->offset, > __clk_get_name(parent), notifiers, > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h > index 3d949c4a3244..2bc0afadf604 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.h > +++ b/drivers/clk/renesas/rcar-gen3-cpg.h > @@ -17,6 +17,7 @@ enum rcar_gen3_clk_types { > CLK_TYPE_GEN3_PLL2, > CLK_TYPE_GEN3_PLL3, > CLK_TYPE_GEN3_PLL4, > + CLK_TYPE_GEN3_SDH, > CLK_TYPE_GEN3_SD, > CLK_TYPE_GEN3_R, > CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ > @@ -32,6 +33,9 @@ enum rcar_gen3_clk_types { > CLK_TYPE_GEN3_SOC_BASE, > }; > > +#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ > + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) > + > #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ > DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) > > -- > 2.30.2
diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 5678768ee1f2..351cb9c04f5c 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, /* * SDn Clock */ + +struct clk * __init cpg_sdh_clk_register(const char *name, + void __iomem *sdnckcr, const char *parent_name, + struct raw_notifier_head *notifiers) +{ + /* placeholder during transition */ + return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1); +} + #define CPG_SD_STP_HCK BIT(9) #define CPG_SD_STP_CK BIT(8) diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h index d00c91b116ca..548cb9562f35 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.h +++ b/drivers/clk/renesas/rcar-cpg-lib.h @@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set); +struct clk * __init cpg_sdh_clk_register(const char *name, + void __iomem *sdnckcr, const char *parent_name, + struct raw_notifier_head *notifiers); + struct clk * __init cpg_sd_clk_register(const char *name, void __iomem *base, unsigned int offset, const char *parent_name, struct raw_notifier_head *notifiers, bool skip_first); diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 558191c99b48..182b189bc8f4 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -486,6 +486,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, mult *= 2; break; + case CLK_TYPE_GEN3_SDH: + return cpg_sdh_clk_register(core->name, base + core->offset, + __clk_get_name(parent), notifiers); + case CLK_TYPE_GEN3_SD: return cpg_sd_clk_register(core->name, base, core->offset, __clk_get_name(parent), notifiers, diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 3d949c4a3244..2bc0afadf604 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -17,6 +17,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PLL2, CLK_TYPE_GEN3_PLL3, CLK_TYPE_GEN3_PLL4, + CLK_TYPE_GEN3_SDH, CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ @@ -32,6 +33,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_SOC_BASE, }; +#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) + #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)