| Message ID | 20211110191610.5664-7-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk/mmc: renesas_sdhi: refactor SDnH to be a separate clock | expand |
CC clk On Wed, Nov 10, 2021 at 8:16 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > We handle it differently meanwhile. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Changes since RFC v1: > * fixed subject prefix > * added tag from Geert > > drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++------------ > 1 file changed, 3 insertions(+), 12 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index aa0797b98e89..c4b36c90e159 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -397,29 +397,20 @@ static u32 cpg_quirks __initdata; > > #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ > #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ > -#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ > > > static const struct soc_device_attribute cpg_quirks_match[] __initconst = { > { > .soc_id = "r8a7795", .revision = "ES1.0", > - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), > + .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), > }, > { > .soc_id = "r8a7795", .revision = "ES1.*", > - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), > - }, > - { > - .soc_id = "r8a7795", .revision = "ES2.0", > - .data = (void *)SD_SKIP_FIRST, > + .data = (void *)(RCKCR_CKSEL), > }, > { > .soc_id = "r8a7796", .revision = "ES1.0", > - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), > - }, > - { > - .soc_id = "r8a7796", .revision = "ES1.1", > - .data = (void *)SD_SKIP_FIRST, > + .data = (void *)(RCKCR_CKSEL), > }, > { /* sentinel */ } > }; > -- > 2.30.2
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index aa0797b98e89..c4b36c90e159 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -397,29 +397,20 @@ static u32 cpg_quirks __initdata; #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ -#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { .soc_id = "r8a7795", .revision = "ES1.0", - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), + .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), }, { .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), - }, - { - .soc_id = "r8a7795", .revision = "ES2.0", - .data = (void *)SD_SKIP_FIRST, + .data = (void *)(RCKCR_CKSEL), }, { .soc_id = "r8a7796", .revision = "ES1.0", - .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), - }, - { - .soc_id = "r8a7796", .revision = "ES1.1", - .data = (void *)SD_SKIP_FIRST, + .data = (void *)(RCKCR_CKSEL), }, { /* sentinel */ } };