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Thu, 2 Dec 2021 13:49:52 +0000 From: Prathamesh Shete To: , , , , , , , CC: , , Subject: [PATCH v2] mmc: sdhci-tegra: Fix switch to HS400ES mode Date: Thu, 2 Dec 2021 19:19:48 +0530 Message-ID: <20211202134948.18448-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <0a8368f9-8ca2-f01b-2f9e-0c91e3b946f5@intel.com> References: <0a8368f9-8ca2-f01b-2f9e-0c91e3b946f5@intel.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2767baa1-dee4-4dbf-45e4-08d9b59aa0ec X-MS-TrafficTypeDiagnostic: MWHPR12MB1680: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sJzJ27hBFZO4rgA6ttnKLD4YZFuXmtKWo4GlQHqhdI4a/hHfV8MRMa1YrF+gJOJ1hLvLXs49CD/El2Y3mKezqwueI1Kr+SZKqujAkUhUmkjpHqZzZajIR1O/O6UFs+dfkIW9ZxkXoD6AILToW+fmsS65FGUDYuymNAOK/fJbtwfk/yaJcJBVOrsjiykwFLE4QRjtgOvr/OjVuIUElPRtjVmE8CjT2TLJrqbvoN7c9vf/vt17vRGksFoNeF8VcLVa+X4waVHwPkmSoY15p07qeCNFVgdM5eHMJgFtrmEJCmgVmpfU228HPATsr8q/GLyeZcgZJvsG9DPSG3MAxcHidznoV4dJ2lzZ5tYvQLUeGQ/k82WTKtLsn7Jp3e/8UolZR/2k28rEAu64Oxnj5OybBS2E5rLNycty+QnzPqKmjhjG7QTZdqV1ovWhwEyw+V4NBMio57m1FR2+X/4sRhK3K7Km4D4+rdozMWA18/AYY1viGi5YG1/68Kc7hFJRvc8iKE+v/h4MZTij+Z2f2kumvL95HgabXERq/eZRdkh1dY7//cMlCGQhonwWFCdXoj98Aqwnn7uKlR8pIhCaeWCmWiP0RSZCeK8DYo+H0UK15aRy9BB9ZqgKI8Nr0JjMOjOHJruLZ45XQDE+Df1h5LtcEjKVRwZ/PFeBzsGFGhXtYisqetjkzUovBVzkbu1c0zq31ppNX0BJUF2GJlHja11vGBBto6AD6dqvlVBb/A7V1E8yu1XzWjhROtTTE4o3orewl3CGfv/GCX9Zfe+hg8E35Q== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(6666004)(8676002)(356005)(54906003)(2616005)(86362001)(82310400004)(1076003)(36860700001)(5660300002)(110136005)(186003)(36756003)(7696005)(316002)(70206006)(107886003)(83380400001)(508600001)(26005)(47076005)(8936002)(2906002)(4326008)(426003)(7636003)(336012)(40460700001)(70586007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 13:49:57.7304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2767baa1-dee4-4dbf-45e4-08d9b59aa0ec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1680 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When CMD13 is sent after switching to HS400ES mode, the bus is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host controller CAR clock and the interface clock are rate matched. Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 43 ++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 387ce9cdbd7c..ca261cce9b37 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -354,23 +354,6 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) } } -static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, - struct mmc_ios *ios) -{ - struct sdhci_host *host = mmc_priv(mmc); - u32 val; - - val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); - - if (ios->enhanced_strobe) - val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; - else - val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; - - sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); - -} - static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -791,6 +774,32 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) } } +static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + u32 val; + + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); + + if (ios->enhanced_strobe) + val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; + else + val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; + + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); + + /* + * When CMD13 is sent from mmc_select_hs400es() after + * switching to HS400ES mode, the bus is operating at + * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. + * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI + * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host + * controller CAR clock and the interface clock are rate matched. + */ + tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); +} + static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);