diff mbox series

[3/4] mmc: mmci: stm32: clear DLYB_CR after sending tuning command

Message ID 20211215141727.4901-4-yann.gautier@foss.st.com (mailing list archive)
State New, archived
Headers show
Series mmc: mmci: updates for STM32MP13 | expand

Commit Message

Yann Gautier Dec. 15, 2021, 2:17 p.m. UTC
During test campaign, and especially after several unbind/bind sequences,
it has been seen that the SD-card on SDMMC1 thread could freeze.
The freeze always appear on a CMD23 following a CMD19.
Checking SDMMC internal registers shows that the tuning command (CMD19)
has failed.
The freeze is then due to the delay block involved in the tuning sequence.
To correct this, clear the delay block register DLYB_CR register after
the tuning commands.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
---
 drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Marek Vasut Dec. 16, 2021, 9:13 a.m. UTC | #1
On 12/15/21 15:17, Yann Gautier wrote:
> During test campaign, and especially after several unbind/bind sequences,
> it has been seen that the SD-card on SDMMC1 thread could freeze.
> The freeze always appear on a CMD23 following a CMD19.
> Checking SDMMC internal registers shows that the tuning command (CMD19)
> has failed.
> The freeze is then due to the delay block involved in the tuning sequence.
> To correct this, clear the delay block register DLYB_CR register after
> the tuning commands.
> 
> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
> ---
>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
> index fdaa11f92fe6..a75d3dd34d18 100644
> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
>   		return -EINVAL;
>   	}
>   
> +	writel_relaxed(0, dlyb->base + DLYB_CR);
> +
>   	phase = end_of_len - max_len / 2;
>   	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);

Shouldn't this have a Fixes: tag and be CC stable ?
This seems like a bugfix, no ?
Yann Gautier Dec. 16, 2021, 9:48 a.m. UTC | #2
On 12/16/21 10:13 AM, Marek Vasut wrote:
> On 12/15/21 15:17, Yann Gautier wrote:
>> During test campaign, and especially after several unbind/bind sequences,
>> it has been seen that the SD-card on SDMMC1 thread could freeze.
>> The freeze always appear on a CMD23 following a CMD19.
>> Checking SDMMC internal registers shows that the tuning command (CMD19)
>> has failed.
>> The freeze is then due to the delay block involved in the tuning 
>> sequence.
>> To correct this, clear the delay block register DLYB_CR register after
>> the tuning commands.
>>
>> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
>> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
>> ---
>>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c 
>> b/drivers/mmc/host/mmci_stm32_sdmmc.c
>> index fdaa11f92fe6..a75d3dd34d18 100644
>> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
>> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
>> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct 
>> mmci_host *host, u32 opcode)
>>           return -EINVAL;
>>       }
>> +    writel_relaxed(0, dlyb->base + DLYB_CR);
>> +
>>       phase = end_of_len - max_len / 2;
>>       sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
> 
> Shouldn't this have a Fixes: tag and be CC stable ?
> This seems like a bugfix, no ?

Hi Marek,

You're right, I should have added:
Fixes: 1103f807a3b9 ("mmc: mmci_sdmmc: Add execute tuning with delay block")

Ulf, could you manage that, or should I push a new version?


Best regards,
Yann
Ulf Hansson Dec. 21, 2021, 1:02 p.m. UTC | #3
On Thu, 16 Dec 2021 at 10:49, Yann Gautier <yann.gautier@foss.st.com> wrote:
>
> On 12/16/21 10:13 AM, Marek Vasut wrote:
> > On 12/15/21 15:17, Yann Gautier wrote:
> >> During test campaign, and especially after several unbind/bind sequences,
> >> it has been seen that the SD-card on SDMMC1 thread could freeze.
> >> The freeze always appear on a CMD23 following a CMD19.
> >> Checking SDMMC internal registers shows that the tuning command (CMD19)
> >> has failed.
> >> The freeze is then due to the delay block involved in the tuning
> >> sequence.
> >> To correct this, clear the delay block register DLYB_CR register after
> >> the tuning commands.
> >>
> >> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
> >> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
> >> ---
> >>   drivers/mmc/host/mmci_stm32_sdmmc.c | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> b/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> index fdaa11f92fe6..a75d3dd34d18 100644
> >> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
> >> @@ -441,6 +441,8 @@ static int sdmmc_dlyb_phase_tuning(struct
> >> mmci_host *host, u32 opcode)
> >>           return -EINVAL;
> >>       }
> >> +    writel_relaxed(0, dlyb->base + DLYB_CR);
> >> +
> >>       phase = end_of_len - max_len / 2;
> >>       sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
> >
> > Shouldn't this have a Fixes: tag and be CC stable ?
> > This seems like a bugfix, no ?
>
> Hi Marek,
>
> You're right, I should have added:
> Fixes: 1103f807a3b9 ("mmc: mmci_sdmmc: Add execute tuning with delay block")
>
> Ulf, could you manage that, or should I push a new version?

Patch applied for fixes and by adding a stable tag too, thanks!

Kind regards
Uffe
diff mbox series

Patch

diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index fdaa11f92fe6..a75d3dd34d18 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -441,6 +441,8 @@  static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
 		return -EINVAL;
 	}
 
+	writel_relaxed(0, dlyb->base + DLYB_CR);
+
 	phase = end_of_len - max_len / 2;
 	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);