Message ID | 20211215141727.4901-5-yann.gautier@foss.st.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | mmc: mmci: updates for STM32MP13 | expand |
On 12/15/21 15:17, Yann Gautier wrote: > Use feedback clock for HS200 mode, as for SDR104. > The HS200 mode can be enabled through DT by using mmc-hs200-1_8v. > It is possible to use it on STM32MP13, but not STM32MP15 platforms. HS200 is possible even on the MP15, it just doesn't yield any (performance) benefits due to the slower bus clock (125 MHz or so?), so it isn't worth enabling it on MP15. It is nice to see MP13 can do better.
On 12/16/21 10:14 AM, Marek Vasut wrote: > On 12/15/21 15:17, Yann Gautier wrote: >> Use feedback clock for HS200 mode, as for SDR104. >> The HS200 mode can be enabled through DT by using mmc-hs200-1_8v. >> It is possible to use it on STM32MP13, but not STM32MP15 platforms. > > HS200 is possible even on the MP15, it just doesn't yield any > (performance) benefits due to the slower bus clock (125 MHz or so?), so > it isn't worth enabling it on MP15. It is nice to see MP13 can do better. Hi Marek, There is a limitation on MP15, please see errata sheet [1], chapter 2.3.19. HS200 (and SDR104) shouldn't be enabled on MP15. Best regards, Yann [1] https://www.st.com/resource/en/errata_sheet/dm00516256.pdf
On 12/16/21 10:44, Yann Gautier wrote: > On 12/16/21 10:14 AM, Marek Vasut wrote: >> On 12/15/21 15:17, Yann Gautier wrote: >>> Use feedback clock for HS200 mode, as for SDR104. >>> The HS200 mode can be enabled through DT by using mmc-hs200-1_8v. >>> It is possible to use it on STM32MP13, but not STM32MP15 platforms. >> >> HS200 is possible even on the MP15, it just doesn't yield any >> (performance) benefits due to the slower bus clock (125 MHz or so?), >> so it isn't worth enabling it on MP15. It is nice to see MP13 can do >> better. > > Hi Marek, > > There is a limitation on MP15, please see errata sheet [1], chapter 2.3.19. > HS200 (and SDR104) shouldn't be enabled on MP15. > > Best regards, > Yann > > [1] https://www.st.com/resource/en/errata_sheet/dm00516256.pdf Oh, I see, so I was lucky to even ever get it working at all. Thanks for the info.
diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c index a75d3dd34d18..9c13f2c31365 100644 --- a/drivers/mmc/host/mmci_stm32_sdmmc.c +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c @@ -241,11 +241,12 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired) /* * SDMMC_FBCK is selected when an external Delay Block is needed - * with SDR104. + * with SDR104 or HS200. */ if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) { clk |= MCI_STM32_CLK_BUSSPEED; - if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) { + if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 || + host->mmc->ios.timing == MMC_TIMING_MMC_HS200) { clk &= ~MCI_STM32_CLK_SEL_MSK; clk |= MCI_STM32_CLK_SELFBCK; }