Message ID | 20220920123752.21027-1-pshete@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3,1/4] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data | expand |
On 20/09/22 15:37, Prathamesh Shete wrote: > Create new SoC data structure for Tegra234 platforms. > Additional features, tap value configurations are added/ > updated for Tegra234 platform hence separate Tegra194 and > Tegra234 SoC data. > > Signed-off-by: Aniruddha Tvs Rao <anrao@nvidia.com> > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 2d2d8260c681..a6c5bbae77b4 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { > .max_tap_delay = 139, > }; > > +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { > + .pdata = &sdhci_tegra186_pdata, > + .dma_mask = DMA_BIT_MASK(39), > + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | > + NVQUIRK_HAS_PADCALIB | > + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | > + NVQUIRK_ENABLE_SDR50 | > + NVQUIRK_ENABLE_SDR104 | > + NVQUIRK_HAS_TMCLK, > + .min_tap_delay = 95, > + .max_tap_delay = 111, > +}; > + > static const struct of_device_id sdhci_tegra_dt_match[] = { > + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, > { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, > { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, > { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },