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Tue, 20 Sep 2022 05:38:06 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 20 Sep 2022 05:38:05 -0700 Received: from pshete-ubuntu.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Tue, 20 Sep 2022 05:38:02 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v3 3/4] mmc: sdhci-tegra: Issue CMD and DAT resets together Date: Tue, 20 Sep 2022 18:07:51 +0530 Message-ID: <20220920123752.21027-3-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220920123752.21027-1-pshete@nvidia.com> References: <20220920123752.21027-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT086:EE_|SN7PR12MB6791:EE_ X-MS-Office365-Filtering-Correlation-Id: d180fc3c-c5f7-4c81-1cb2-08da9b05081f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2022 12:38:33.8182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d180fc3c-c5f7-4c81-1cb2-08da9b05081f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6791 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. SDHCI controller FSM goes into bad state due to rapid SD card hot-plug event. Issuing reset on the CMD FSM before DATA FSM results in kernel panic, hence add support to issue CMD and DAT resets together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 20 +++++++++++++++----- drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 4d32b5bfc424..58449e010a9b 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1532,7 +1532,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7689ffec5ad1..2f4a0e84fee8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3060,12 +3060,22 @@ static bool sdhci_request_done(struct sdhci_host *host) host->ops->set_clock(host, host->clock); /* - * Spec says we should do both at the same time, but Ricoh - * controllers do not like that. + * While the specification says we should do both at the + * same time, Ricoh controllers (and potentially others) do not + * like that. On the other hand, some controllers (such as those + * found on Tegra186 and later) rely on both being reset at the + * same time. Use a quirk for the latter category since most + * controllers seem to work fine with DAT and CMD getting reset + * at the same time. */ - sdhci_do_reset(host, SDHCI_RESET_CMD); - sdhci_do_reset(host, SDHCI_RESET_DATA); - + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | + SDHCI_RESET_DATA); + } else { + sdhci_do_reset(host, SDHCI_RESET_CMD); + sdhci_do_reset(host, SDHCI_RESET_DATA); + } host->pending_reset = false; } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 95a08f09df30..8045308f7859 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -480,6 +480,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */