| Message ID | 20221006130622.22900-4-pshete@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v7,1/4] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data | expand |
On Thu, 6 Oct 2022 at 15:07, Prathamesh Shete <pshete@nvidia.com> wrote: > > Ensure tegra_host member "curr_clk_rate" holds the actual clock rate > instead of requested clock rate for proper use during tuning correction > algorithm. Actual clk rate may not be the same as the requested clk > frequency depending on the parent clock source set. Tuning correction > algorithm depends on certain parameters which are sensitive to current > clk rate. If the host clk is selected instead of the actual clock rate, > tuning correction algorithm may end up applying invalid correction, > which could result in errors > > Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") > > Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com> > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> > Acked-by: Thierry Reding <treding@nvidia.com> Applied for fixes and by adding a stable tag, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-tegra.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 3663c5d0efe0..ccbb26a66284 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -783,7 +783,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) > dev_err(dev, "failed to set clk rate to %luHz: %d\n", > host_clk, err); > > - tegra_host->curr_clk_rate = host_clk; > + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); > if (tegra_host->ddr_signaling) > host->max_clk = host_clk; > else > -- > 2.17.1 >
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 3663c5d0efe0..ccbb26a66284 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -783,7 +783,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) dev_err(dev, "failed to set clk rate to %luHz: %d\n", host_clk, err); - tegra_host->curr_clk_rate = host_clk; + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); if (tegra_host->ddr_signaling) host->max_clk = host_clk; else
Ensure tegra_host member "curr_clk_rate" holds the actual clock rate instead of requested clock rate for proper use during tuning correction algorithm. Actual clk rate may not be the same as the requested clk frequency depending on the parent clock source set. Tuning correction algorithm depends on certain parameters which are sensitive to current clk rate. If the host clk is selected instead of the actual clock rate, tuning correction algorithm may end up applying invalid correction, which could result in errors Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)