From patchwork Wed Oct 19 21:54:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13012358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC24EC433FE for ; Wed, 19 Oct 2022 21:55:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231500AbiJSVzh (ORCPT ); Wed, 19 Oct 2022 17:55:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231433AbiJSVzT (ORCPT ); Wed, 19 Oct 2022 17:55:19 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E27C3743F for ; Wed, 19 Oct 2022 14:55:16 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id q1so17457245pgl.11 for ; Wed, 19 Oct 2022 14:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mdWjXp1yQqqnWhAF+f3RrVqI4HKKxf+i6fXlj1bwLGc=; b=dsorLnZ6g7l46LRyLdlp2vDy2D5bxCKpUlzS+ILZbL2KnQEvI9+bHKJsmLlMd5z939 vFlptL1Scv3wg1kkesMKClNuMREJqrHJ2b1uLX9NPxSkw4qQzeJLAYCuENPkiEgsu5qq +DWF967Wz8uWOX1fu5humVdZ0fo80sExLbdRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mdWjXp1yQqqnWhAF+f3RrVqI4HKKxf+i6fXlj1bwLGc=; b=rau1vrZAVnhpY7ojmWGzK8JdnMOgCdRt0QC8Q9eZBuuoFHR/3JvCwUQAzeJ49jfWmE 30XpE6RXE89WbH+Zr7WDgCUX6vxKEEDC10hMu29XasEoGc6/RBwbFW19x1kfnx0Q3PaQ BGrJ/Sxlp5mIWxKuWQhNVcE2V4+tCm/1n3kTCChXL8hT5egBYHl3fcy2Hq6XIKJHx4ri YBLPqeLIVl7ZfXuRNCHBrs5K5DQ7/dsfjRaIsiihDJiQarxzLxCS8V1vzZSH3rjCODaM A8q2fTr5Qx9e2pWQJRaKrvcQrucy6DHKsrgpCQ0espqUQlhCh+K/ChBBpdu/1zPV9uP1 XQWA== X-Gm-Message-State: ACrzQf0futxJ5Aa/YtzuOA5q9B05A+PntGLZPUMkTcu5N3IdMR4qyAdB NtFInCAiNOlAovSSVXJMpbhZHA== X-Google-Smtp-Source: AMsMyM7ucaMeh7aA0C9osOktHedzsvrEuCvV5oZ+DjVR9lNos2N3qyUSnVuMThWXyLgLD5alo3A/wA== X-Received: by 2002:a05:6a00:408c:b0:565:fc2c:8c71 with SMTP id bw12-20020a056a00408c00b00565fc2c8c71mr10838457pfb.82.1666216514655; Wed, 19 Oct 2022 14:55:14 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:57b7:1f0e:44d1:f252]) by smtp.gmail.com with UTF8SMTPSA id c4-20020a633504000000b0043be67b6304sm10453631pga.0.2022.10.19.14.55.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Oct 2022 14:55:14 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Shawn Guo , Fabio Estevam , Haibo Chen , Broadcom internal kernel review list , NXP Linux Team , Pengutronix Kernel Team , Florian Fainelli , Michal Simek , Faiz Abbas , linux-mmc@vger.kernel.org, Jonathan Hunter , Al Cooper , linux-arm-kernel@lists.infradead.org, Sowjanya Komatineni , linux-kernel@vger.kernel.org, Thierry Reding , Adrian Hunter , Sascha Hauer , Brian Norris Subject: [PATCH v2 6/7] mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCI Date: Wed, 19 Oct 2022 14:54:39 -0700 Message-Id: <20221019145246.v2.6.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221019215440.277643-1-briannorris@chromium.org> References: <20221019215440.277643-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Signed-off-by: Brian Norris --- (no changes since v1) drivers/mmc/host/sdhci_am654.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8f1023480e12..187a21086791 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -378,6 +378,9 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {