From patchwork Mon Oct 24 17:54:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13018029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA196C38A2D for ; Mon, 24 Oct 2022 19:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231826AbiJXTWt (ORCPT ); Mon, 24 Oct 2022 15:22:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231975AbiJXTVv (ORCPT ); Mon, 24 Oct 2022 15:21:51 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2666A17FD59 for ; Mon, 24 Oct 2022 10:57:06 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id r61-20020a17090a43c300b00212f4e9cccdso4618552pjg.5 for ; Mon, 24 Oct 2022 10:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hDRHGSwf7KM6nOlEftMlpWT5HOavgsCjZBMurS4KgKQ=; b=N7qZz/zJfn8lrPYDgaQNbAKG2AbnWZeyNQLBZ7DHtw0LYdnjsr6ZX1FDH55nDDkMIo UcqYTJ9Nprz+nvahXLqZBr+tO2XbMHIwASvchpoIo1YliHu11CIR9y4k65EolzPxGa4N gtKpf+WRwwqv/Gv/eyY9jWWqok8HVyLx+4LSE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hDRHGSwf7KM6nOlEftMlpWT5HOavgsCjZBMurS4KgKQ=; b=f1bUHeUxN25IqgtZWoLn5bKB2LCaM+W+Bj4Y0QNT8khl2yGMRCQSlhZJMCGxBtXAGh CqwwbaRGDw3ADJf8qdJfImltyQqp+R4qORWzBcHlEnL9ZWceKHOXlOiklbpwf5+FEdos fLrz+ZtoMwqwTjznUew5jnobIIpSmGqM/RFi9vGmgqTNuByUCRiq0QnfFpuWpza/rIJ7 Xqfn3zYV/ascds302HlOjhzjgUQqQJwMIEHx2mDbDVqYlVoe26Sav5nA4tlHD2GlDpyB KHyAZq6TyxNBsYHLyZpUW8zJONmZF08JoZLFzk5OpY0W7GRzrznzN7ZYcZMCBP7RROFd Y/Sg== X-Gm-Message-State: ACrzQf37CNw9DhkZpLxsFr9ZNa6a/qqEG2l2oysi33qnFqeQmCaV9Z/v 5oJ9t7IBO9Wb+My+Z61fsQGwYg== X-Google-Smtp-Source: AMsMyM5BthOgJGA3ADerm/sDHRlf1tA0MU33oqIWE/gleggB4VstlKI4Rnx87QJKBubqXVFGk/KMNg== X-Received: by 2002:a17:90a:c306:b0:211:8e5e:9a66 with SMTP id g6-20020a17090ac30600b002118e5e9a66mr29200392pjt.152.1666634183551; Mon, 24 Oct 2022 10:56:23 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id mr2-20020a17090b238200b0021301a63e86sm2386229pjb.18.2022.10.24.10.56.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:23 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris Subject: [PATCH v3 4/7] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:58 -0700 Message-Id: <20221024105229.v3.4.I7d01f9ad11bacdc9213dee61b7918982aea39115@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Brian Norris Reviewed-by: Haibo Chen Acked-by: Adrian Hunter --- Changes in v3: - Use new SDHCI+CQHCI helper - Add Reviewed-by Changes in v2: - Drop unnecessary ESDHC_FLAG_CQHCI check drivers/mmc/host/sdhci-esdhc-imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 55981b0f0b10..b297c3c360eb 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -25,6 +25,7 @@ #include #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" #include "cqhci.h" @@ -1288,7 +1289,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) static void esdhc_reset(struct sdhci_host *host, u8 mask) { - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);