From patchwork Tue Oct 25 13:29:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 13019238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A098ECDFA1 for ; Tue, 25 Oct 2022 13:30:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232847AbiJYNaP (ORCPT ); Tue, 25 Oct 2022 09:30:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232662AbiJYNaL (ORCPT ); Tue, 25 Oct 2022 09:30:11 -0400 Received: from mxout3.routing.net (mxout3.routing.net [IPv6:2a03:2900:1:a::8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 394FBDEF25; Tue, 25 Oct 2022 06:30:02 -0700 (PDT) Received: from mxbox1.masterlogin.de (unknown [192.168.10.88]) by mxout3.routing.net (Postfix) with ESMTP id 9F3AD6269B; Tue, 25 Oct 2022 13:30:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1666704600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bMnJc+k3BQCb5bXYfRL3MsvClm+VDOd3dvG9NLKDvOQ=; b=bqmjXLDAHMMTdEesmQZpRVjFUesGHRW4pFIElh7RlDZ3fk2PHkd3CB6WZcs0tUkYoyeic2 ZMfInO8tsZY1OT3/41+sXPu0C46qltffdlN69AXlPNukYwyOpyYQUCwW8Tn0gGEh3gYlm0 66CrMJL7mR/wOBgeD2FvM08GgIvhxWw= Received: from frank-G5.. (fttx-pool-217.61.152.57.bambit.de [217.61.152.57]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id B857340112; Tue, 25 Oct 2022 13:29:59 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Chaotian Jing , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Wenbin Mei , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sam Shih , Sam Shih Subject: [PATCH v5 2/6] dt-bindings: mmc: Add support for Mediatek MT7986 Date: Tue, 25 Oct 2022 15:29:49 +0200 Message-Id: <20221025132953.81286-3-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221025132953.81286-1-linux@fw-web.de> References: <20221025132953.81286-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: a777fd38-8390-4268-8bed-ccfa143c1ccc Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Sam Shih This commit adds dt-binding documentation of mmc for Mediatek MT7986 SoC Platform. Add SoC specific section for defining clock configuration. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- v3: - drop assigned-clocks/assigned-clock-parents - fix clock description v4: - update binding for mt7986 (new mtk version) - squashed part 1 (compatible) and 3 (SoC specific clock config) and so dropped Ack from Rob for 1rst Part v5: - drop quotes around clock names --- .../devicetree/bindings/mmc/mtk-sd.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 0cedeb12892d..6f8ecb4788eb 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt6795-mmc - mediatek,mt7620-mmc - mediatek,mt7622-mmc + - mediatek,mt7986-mmc - mediatek,mt8135-mmc - mediatek,mt8173-mmc - mediatek,mt8183-mmc @@ -237,6 +238,31 @@ allOf: reg: minItems: 2 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt7986-mmc + then: + properties: + clocks: + minItems: 3 + items: + - description: source clock + - description: HCLK which used for host + - description: independent source clock gate + - description: bus clock used for internal register access (required for MSDC0/3). + - description: msdc subsys clock gate + clock-names: + minItems: 3 + items: + - const: source + - const: hclk + - const: source_cg + - const: bus_clk + - const: sys_cg + - if: properties: compatible: