| Message ID | 20221026124150.v4.6.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: sdhci controllers: Fix SDHCI_RESET_ALL for CQHCI | expand |
On 26/10/22 22:42, Brian Norris wrote: > [[ NOTE: this is completely untested by the author, but included solely > because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix > SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other > drivers using CQHCI might benefit from a similar change, if they > also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same > bug on at least MSM, Arasan, and Intel hardware. ]] > > SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't > tracking that properly in software. When out of sync, we may trigger > various timeouts. > > It's not typical to perform resets while CQE is enabled, but this may > occur in some suspend or error recovery scenarios. > > Include this fix by way of the new sdhci_and_cqhci_reset() helper. > > This patch depends on (and should not compile without) the patch > entitled "mmc: cqhci: Provide helper for resetting both SDHCI and > CQHCI". > > Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") > Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > > Changes in v4: > - Also fix sdhci_am654_ops, sdhci_j721e_8bit_ops > - Add dependency notes > - Drop bouncing Faiz Abbas <faiz_abbas@ti.com> address > > Changes in v3: > - Use new SDHCI+CQHCI helper > > drivers/mmc/host/sdhci_am654.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c > index 8f1023480e12..c2333c7acac9 100644 > --- a/drivers/mmc/host/sdhci_am654.c > +++ b/drivers/mmc/host/sdhci_am654.c > @@ -15,6 +15,7 @@ > #include <linux/sys_soc.h> > > #include "cqhci.h" > +#include "sdhci-cqhci.h" > #include "sdhci-pltfm.h" > > /* CTL_CFG Registers */ > @@ -378,7 +379,7 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); > > - sdhci_reset(host, mask); > + sdhci_and_cqhci_reset(host, mask); > > if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { > ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); > @@ -464,7 +465,7 @@ static struct sdhci_ops sdhci_am654_ops = { > .set_clock = sdhci_am654_set_clock, > .write_b = sdhci_am654_write_b, > .irq = sdhci_am654_cqhci_irq, > - .reset = sdhci_reset, > + .reset = sdhci_and_cqhci_reset, > }; > > static const struct sdhci_pltfm_data sdhci_am654_pdata = { > @@ -494,7 +495,7 @@ static struct sdhci_ops sdhci_j721e_8bit_ops = { > .set_clock = sdhci_am654_set_clock, > .write_b = sdhci_am654_write_b, > .irq = sdhci_am654_cqhci_irq, > - .reset = sdhci_reset, > + .reset = sdhci_and_cqhci_reset, > }; > > static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8f1023480e12..c2333c7acac9 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -15,6 +15,7 @@ #include <linux/sys_soc.h> #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" /* CTL_CFG Registers */ @@ -378,7 +379,7 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); @@ -464,7 +465,7 @@ static struct sdhci_ops sdhci_am654_ops = { .set_clock = sdhci_am654_set_clock, .write_b = sdhci_am654_write_b, .irq = sdhci_am654_cqhci_irq, - .reset = sdhci_reset, + .reset = sdhci_and_cqhci_reset, }; static const struct sdhci_pltfm_data sdhci_am654_pdata = { @@ -494,7 +495,7 @@ static struct sdhci_ops sdhci_j721e_8bit_ops = { .set_clock = sdhci_am654_set_clock, .write_b = sdhci_am654_write_b, .irq = sdhci_am654_cqhci_irq, - .reset = sdhci_reset, + .reset = sdhci_and_cqhci_reset, }; static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
[[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Signed-off-by: Brian Norris <briannorris@chromium.org> --- Changes in v4: - Also fix sdhci_am654_ops, sdhci_j721e_8bit_ops - Add dependency notes - Drop bouncing Faiz Abbas <faiz_abbas@ti.com> address Changes in v3: - Use new SDHCI+CQHCI helper drivers/mmc/host/sdhci_am654.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)