| Message ID | 20221114230217.202634-1-dinguyen@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PATCHv9,1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" | expand |
On Mon, 14 Nov 2022 17:02:12 -0600, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v9: remove required for "altr,sysmgr-syscon" > v8: remove "" around synopsys-dw-mshc-common.yaml# > v7: and "not" for the required "altr,sysmgr-syscon" binding > v6: make "altr,sysmgr-syscon" optional > v5: document reg shift > v4: add else statement > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- > 1 file changed, 29 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Tue, 15 Nov 2022 at 00:02, Dinh Nguyen <dinguyen@kernel.org> wrote: > > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Applied for next, thanks! Kind regards Uffe > --- > v9: remove required for "altr,sysmgr-syscon" > v8: remove "" around synopsys-dw-mshc-common.yaml# > v7: and "not" for the required "altr,sysmgr-syscon" binding > v6: make "altr,sysmgr-syscon" optional > v5: document reg shift > v4: add else statement > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- > 1 file changed, 29 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > index ae6d6fca79e2..e1f5f26f3f1c 100644 > --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > > title: Synopsys Designware Mobile Storage Host Controller Binding > > -allOf: > - - $ref: "synopsys-dw-mshc-common.yaml#" > - > maintainers: > - Ulf Hansson <ulf.hansson@linaro.org> > > @@ -38,6 +35,35 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + - description: register shift for the smplsel(drive in) setting > + description: > + This property is optional. Contains the phandle to System Manager block > + that contains the SDMMC clock-phase control register. The first value is > + the pointer to the sysmgr, the 2nd value is the register offset for the > + SDMMC clock phase register, and the 3rd value is the bit shift for the > + smplsel(drive in) setting. > + > +allOf: > + - $ref: synopsys-dw-mshc-common.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: altr,socfpga-dw-mshc > + then: > + properties: > + altr,sysmgr-syscon: true > + else: > + properties: > + altr,sysmgr-syscon: false > + > required: > - compatible > - reg > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..e1f5f26f3f1c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -38,6 +35,35 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + This property is optional. Contains the phandle to System Manager block + that contains the SDMMC clock-phase control register. The first value is + the pointer to the sysmgr, the 2nd value is the register offset for the + SDMMC clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + properties: + altr,sysmgr-syscon: true + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg
Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v9: remove required for "altr,sysmgr-syscon" v8: remove "" around synopsys-dw-mshc-common.yaml# v7: and "not" for the required "altr,sysmgr-syscon" binding v6: make "altr,sysmgr-syscon" optional v5: document reg shift v4: add else statement v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-)